JPS645544U - - Google Patents

Info

Publication number
JPS645544U
JPS645544U JP9942287U JP9942287U JPS645544U JP S645544 U JPS645544 U JP S645544U JP 9942287 U JP9942287 U JP 9942287U JP 9942287 U JP9942287 U JP 9942287U JP S645544 U JPS645544 U JP S645544U
Authority
JP
Japan
Prior art keywords
circuit
signal
test signal
test
common
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9942287U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP9942287U priority Critical patent/JPS645544U/ja
Publication of JPS645544U publication Critical patent/JPS645544U/ja
Pending legal-status Critical Current

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  • Time-Division Multiplex Systems (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの考案の一実施例による信号変換イ
ンタフエース部折返し試験方式を示すブロツク図
、第2図は従来の信号変換インタフエース部折返
し試験方式を示すブロツク図である。 1は折返し試験回路、2,3は信号変換インタ
フエース部、6,7は試験信号発信回路、9,1
0は試験信号受信回路、12,13は信号変換回
路、14は共通試験信号発信回路、15は応答信
号受信回路、16,17は共通試験信号受信回路
、18,19は応答信号発信回路。なお、図中、
同一符号は同一、又は相当部分を示す。
FIG. 1 is a block diagram showing a signal conversion interface section loopback test method according to an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional signal conversion interface section loopback test method. 1 is a return test circuit, 2 and 3 are signal conversion interface sections, 6 and 7 are test signal transmission circuits, 9 and 1
0 is a test signal receiving circuit, 12 and 13 are signal conversion circuits, 14 is a common test signal transmitting circuit, 15 is a response signal receiving circuit, 16 and 17 are common test signal receiving circuits, and 18 and 19 are response signal transmitting circuits. In addition, in the figure,
The same reference numerals indicate the same or corresponding parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 各種属性をもつ外部信号を内部多重バスに信号
変換するため、それぞれの属性毎に用意された信
号変換インタフエース部と、この信号変換インタ
フエース部の正常性を試験する折返し試験回路を
備えたデジタル多重装置において、前記各信号変
換インタフエース部は、それが有する属性用の試
験信号を発信する試験信号発信回路と、信号変換
回路で折返された前記試験信号を受信する試験信
号受信回路と、共通試験信号を受信して前記試験
信号発信回路を起動する共通試験信号受信回路と
、前記試験信号を受信した前記試験信号受信回路
に起動されて応答信号を発信する応答信号発信回
路を備え、前記折返し試験回路は、前記共通試験
信号を発信する共通試験信号発信回路と、返送さ
れてくる前記応答信号を受信する応答信号受信回
路を備えたことを特徴とするデジタル多重装置。
In order to convert external signals with various attributes to an internal multiplex bus, the digital converter is equipped with a signal conversion interface section prepared for each attribute and a loopback test circuit to test the normality of this signal conversion interface section. In the multiplexing device, each signal conversion interface section has a common test signal transmission circuit that transmits a test signal for the attribute that it has, and a test signal reception circuit that receives the test signal returned by the signal conversion circuit. a common test signal receiving circuit that receives a test signal and activates the test signal transmitting circuit; and a response signal transmitting circuit that is activated by the test signal receiving circuit that receives the test signal and transmits a response signal; A digital multiplexing device characterized in that the test circuit includes a common test signal transmitting circuit for transmitting the common test signal and a response signal receiving circuit for receiving the returned response signal.
JP9942287U 1987-06-30 1987-06-30 Pending JPS645544U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9942287U JPS645544U (en) 1987-06-30 1987-06-30

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9942287U JPS645544U (en) 1987-06-30 1987-06-30

Publications (1)

Publication Number Publication Date
JPS645544U true JPS645544U (en) 1989-01-12

Family

ID=31326566

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9942287U Pending JPS645544U (en) 1987-06-30 1987-06-30

Country Status (1)

Country Link
JP (1) JPS645544U (en)

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