JPS645493B2 - - Google Patents

Info

Publication number
JPS645493B2
JPS645493B2 JP7845583A JP7845583A JPS645493B2 JP S645493 B2 JPS645493 B2 JP S645493B2 JP 7845583 A JP7845583 A JP 7845583A JP 7845583 A JP7845583 A JP 7845583A JP S645493 B2 JPS645493 B2 JP S645493B2
Authority
JP
Japan
Prior art keywords
frequency
pll
demodulation
digital tuning
phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP7845583A
Other languages
English (en)
Japanese (ja)
Other versions
JPS59204318A (ja
Inventor
Koichi Hirayama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP7845583A priority Critical patent/JPS59204318A/ja
Publication of JPS59204318A publication Critical patent/JPS59204318A/ja
Publication of JPS645493B2 publication Critical patent/JPS645493B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D1/00—Demodulation of amplitude-modulated oscillations
    • H03D1/22—Homodyne or synchrodyne circuits
    • H03D1/2209—Decoders for simultaneous demodulation and decoding of signals composed of a sum-signal and a suppressed carrier, amplitude modulated by a difference signal, e.g. stereocoders
    • H03D1/2236—Decoders for simultaneous demodulation and decoding of signals composed of a sum-signal and a suppressed carrier, amplitude modulated by a difference signal, e.g. stereocoders using a phase locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Circuits Of Receivers In General (AREA)
JP7845583A 1983-05-04 1983-05-04 デジタルチユ−ニング受信機 Granted JPS59204318A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7845583A JPS59204318A (ja) 1983-05-04 1983-05-04 デジタルチユ−ニング受信機

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7845583A JPS59204318A (ja) 1983-05-04 1983-05-04 デジタルチユ−ニング受信機

Publications (2)

Publication Number Publication Date
JPS59204318A JPS59204318A (ja) 1984-11-19
JPS645493B2 true JPS645493B2 (fr) 1989-01-31

Family

ID=13662507

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7845583A Granted JPS59204318A (ja) 1983-05-04 1983-05-04 デジタルチユ−ニング受信機

Country Status (1)

Country Link
JP (1) JPS59204318A (fr)

Also Published As

Publication number Publication date
JPS59204318A (ja) 1984-11-19

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