JPS645493B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an improvement of a digital tuning receiver having a PLL synchronous demodulation function.

[Technical background of the invention and its problems]

As is well known, if a so-called PLL synchronous demodulation circuit is used as a receiving demodulation method for AM broadcasting, distortion will be reduced even if the signal passing bandwidth of the previous stage (for example, an intermediate frequency filter, etc.) is widened compared to normal envelope demodulation. This makes it possible to obtain a high-band demodulated signal without noise or interference.

Therefore, no matter what kind of pre-emphasis characteristics are applied on the transmitting side, on the receiving side the audio amplifier circuit after PLL synchronized demodulation can faithfully reproduce the audio, so it is possible to reproduce high-fidelity AM signals just like FM broadcasters. It is possible to realize a receiver.

In this case, it is also possible to design a standard receiver in which arbitrary demodulation characteristics are specified.

In addition, by performing PLL synchronous demodulation,
Just as it is possible to perform SSB reception without so-called filtering, it is also possible to provide a function to eliminate adjacent station interference while maintaining broadband demodulation characteristics.

Furthermore, the PLL synchronous demodulation circuit is also suitable for demodulating AM stereo signals using various methods.

In this way, if PLL synchronous demodulation is adopted as a demodulation method for AM broadcasting, it will have many features and functions that cannot be obtained with normal envelope demodulation, so such PLL synchronous demodulation will be widely used in AM receivers in the future. It can be said that it has a possibility of being adopted.

However, the PLL synchronous demodulation circuit has a problem in that its circuit configuration is more complex than the envelope demodulation circuit. In this case, in order to support AM stereo demodulation, etc., a high-precision voltage-controlled oscillator with particularly low phase noise is required as one of the circuits constituting the PLL circuit.

In addition, when using a PLL synchronous demodulation circuit,
A unique problem in the manual dial tuning state is that unpleasant beat components are generated from the demodulated output during tuning and detuning, so a circuit to counter these problems is also required.

For this reason, as shown in Figure 1, PLL
It is conceivable to apply a synchronous demodulation circuit.

That is, an input signal to be demodulated from a high frequency stage section (not shown) is converted into a predetermined intermediate frequency signal by a local oscillation signal from a digital tuning section 12, which will be described later, at a mixer 11, and then sent to an intermediate frequency filter 13 and an intermediate frequency signal. will be described later via the amplifier 14.
The signal is guided to the PLL synchronous demodulation circuit section 15.

Here, the digital tuning section 12 is
Based on the PLL method, the reference frequency oscillator 12
1, 1/J frequency divider 122, phase/frequency comparator 1
23, a local frequency oscillator 124, and a 1/N frequency divider 125 which is externally controlled in a variable frequency dividing manner to determine the reception frequency.

And, this digital tuning section 12
In the case of the upper heterodyne, where the receiving frequency is _C , the intermediate frequency is _I , the reference oscillation frequency is _O , and the local oscillation frequency is _L , _L = _C + Digital tuning such that the N division of _I is equal to the J division of _O. It is controlled by the following relationship: _C + _I /N = _O /J ∴ _C = N・_O /J- _I ... (1).

In addition, the PLL synchronous demodulation circuit section 15 outputs an in-phase demodulation output (I-DET・OUT) using an in-phase carrier and an orthogonal demodulation output (Q-DET.OUT) using an orthogonal carrier from the demodulated input signal converted into an intermediate frequency signal.
It has first and second phase detectors 151, 152 and first and second low-pass filters 153, 154 for deriving the in-phase carrier and quadrature carrier, and a PLL circuit 155 for regenerating the in-phase carrier and quadrature carrier. have.

Here, the PLL circuit 155 includes a loop filter 156 that extracts a DC component from the orthogonal demodulated output (Q-DET.OUT), and a voltage-controlled oscillator 157 whose phase is controlled by the DC component from the loop filter 156. , and a Johnson counter 158 which obtains the in-phase carrier and quadrature carrier from the output from the voltage controlled oscillator 157.

This PLL circuit 155 receives an output of 4 _I from the voltage controlled oscillator 157 as an input carrier _I.
The phase is locked to 4 with Johnson counter 158.
By dividing the in-phase (demodulation) carrier cos
(2π _I t) is obtained and given to the first phase comparator 151, and the orthogonal (demodulation) carrier sin
(2π _I t) is obtained and applied to the second phase comparator 152.

In this case, the first and second phase detectors 15
1 and 152 each have a multiplication function.

And the above in-phase demodulation output (I-DET.OUT)
This signal corresponds to the normal AM demodulation output and is sent to the next stage (audio amplifier) not shown.

However, in the configuration of FIG. 1 as described above, the PLL circuit 1 of the PLL synchronous demodulation circuit section
There was a problem in that the circuit cost of the voltage controlled oscillator 157 used in the oscillator 55 was extremely expensive for the following reasons.

First, as mentioned above, the voltage controlled oscillator 157 in this case is designed to reduce phase noise in particular, and to perform AM
One point is that good demodulation characteristics must be obtained even in the case of stereo etc.

In addition, the free-running frequency is set to exactly 4 _I , so that the phase of the demodulated carrier does not deviate from the correct relationship as described above, which deteriorates the demodulation characteristics and causes loss of synchronization and beats at weak inputs. One point is that it is necessary to take measures to prevent reception sensitivity from becoming poor due to the occurrence of this phenomenon.

Furthermore, in order to meet the above-mentioned requirements, it is necessary to make the device highly stable overall, including its temperature characteristics and aging characteristics.

Another problem with this type of voltage controlled oscillator is that it requires the use of variable capacitance diodes, coils, etc., which are generally not suitable for integrated circuit implementation.

[Purpose of the invention]

Therefore, the present invention has been made in view of the above points, and provides an improved digital tuning receiver that has the simplest possible configuration, is inexpensive, and can add a good PLL synchronization demodulation function. It is intended to.

[Summary of the invention]

That is, the digital tuning receiver according to the present invention includes a digital tuning section that converts an input signal to be demodulated into a predetermined intermediate frequency signal using a PLL method, and a digital tuning section that converts an input signal to be demodulated into a predetermined intermediate frequency signal using the PLL method, and a digital tuning section that converts an input signal to be demodulated into a predetermined intermediate frequency signal using the PLL method. A demodulation output and an orthogonal demodulation output are derived, and the output from the reference oscillator of the digital tuning section, which is controlled based on the orthogonal demodulation output, is subjected to frequency division processing so that the frequency is equal to the frequency of the intermediate frequency signal and 90% of each other.゜In-phase carrier and quadrature carrier for demodulation with phase difference
It is characterized by comprising a PLL synchronous demodulation circuit section that performs reproduction using the PLL method.

[Embodiments of the invention]

An embodiment of the present invention will be described in detail below with reference to the drawings.

That is, in FIG. 2, the same reference numerals are given to the parts that are configured similarly to those in FIG. This is a new configuration that differs greatly from that of FIG. 1 in that a reference frequency oscillator 20 is used which also serves as the voltage controlled oscillator 157 in the PLL circuit 155 of the PLL synchronous demodulation circuit section 15.

In this case, the reference frequency oscillator 20 is a voltage-controlled type controlled by the DC output from the loop filter 156 in the PLL circuit 155, but it is not constructed using a variable capacitance diode or the like like a normal voltage-controlled oscillator. , which uses a crystal oscillator and the like as a normal reference oscillator, has extremely high stability.

Then, the reference oscillation frequency _O from the reference oscillator 20 is supplied to the input of the Johnson counter 158 in the PLL circuit 155 via the 1/M frequency divider 21 and the 1/K frequency divider 22. .

Further, the output from the 1/M frequency divider 21 is transferred to the 1/J frequency divider 12 of the digital tuning section 12.
2 inputs.

Next, for convenience in the above configuration, M=1
(However, if M≠1, _O /M may be used.) The operation will be explained below.

First, as described above, in the digital tuning section 12, the local oscillation frequency _L is controlled according to the relationship _L /N= _O /J∴L= _N · _O /J.

As a result, the intermediate frequency _I becomes _I = ±( _L − _C ) = ±(N・_O /J− _C ), and the receiving frequency _C becomes _C =N・_O /J〓 _i ……(2) . In this equation (2), the moment is the upper heterodyne, and the + moment is the lower heterodyne, so it can be seen that it is the same as the above-mentioned equation (1).

In addition, the PLL circuit 1 of the PLL synchronous demodulation circuit section 15
55 further divides the reference oscillation frequency _O by K by 4
Since the reference oscillator 20 is controlled in such a way that the phase is locked so that the divided frequency is equal to the intermediate frequency _I , the relationship is _O /4K= _i ∴ _O =4K _I (3).

In this case, according to equation (2), the change step _ΔC in the reception frequency C corresponding to a one-step change in the variable frequency division number N set by an external controller (not shown) to determine the reception frequency is _{ΔC =} Since _O /J, we have the following relationship: _O = J・_ΔC (4).

In other words, from equations (3) and (4), it is only necessary to select the reference oscillation frequency _O of the digital tuning unit 12 to be a common multiple of 4 _I , which is four times the intermediate frequency _I , and the reception frequency step _ΔC . It turns out.

For example, in the case of a digital tuning receiver for AM broadcasting, the intermediate frequency _I is often 450kHz, so the above condition is _4I = 1.8MHz, so _O is not equal to _ΔC = 9kHz or _ΔC = 10kHz.
Any multiple of 1.8MHz is sufficient.

Next, the operation of the digital tuning receiver to which the PLL synchronous demodulation function as described above is added will be described in a state where the reception frequency is slightly changed. However, this is an example of a case where the receiving frequency is slightly increased in the case of upper heterodyne.

In other words, if the receiving frequency increases slightly,
Since it is an upper heterodyne, the intermediate frequency tends to be lower than _I , but the PLL synchronous demodulation circuit section 15
the reference oscillation frequency _O such that the second phase detector 152 detects it and increases the intermediate frequency _I.
is controlled in the upward direction to increase the local oscillation frequency _L.

As a result, the final intermediate frequency is slightly higher than _I , but the demodulated carrier regenerated by the PLL circuit 155 is also slightly higher than that at steady state due to the rise in _O , so the receiver as a whole is stable. Since the state can be maintained locked, there is no problem.

Also, in the case of the lower heterodyne, when the intermediate frequency _I is about to rise, the second phase detector 152 increases the reference oscillation frequency _O.
Since the reference oscillator 20 is automatically controlled by the output of the reference oscillator 20, it operates in the same manner as in the above case.

In other words, to generalize the above, when the input frequency becomes α _C (however, α is a value close to 1) and the reference frequency is controlled to β _O , the local oscillation frequency at that time is It is controlled so that β _L =N·β _O /J. Therefore, if the intermediate frequency is γ _I , then the relationship is as follows: γ _I =±(β _L −α _C ) =±(N·β _O /J−α _C ) ……(5).

Also, at this time, the PLL synchronous demodulation circuit section 15
The PLL circuit 155 outputs the reference frequency oscillator 1 so that the 4K divided output of the reference oscillation frequency β _O is equal to equation (5).
57, β _O /4K = γ _I ∴β _O = γ・4K _I ...(6). In this case, since 4K _I = _O from equation (3), equation (6) becomes β _O = γ _O ∴ β = γ ... (7).

Then, by substituting _C given by equation (2) into equation (5), we get γ _I =±(N・β _O /J−N・α _O /J±α _i
) = α _I ∴ γ = α ...(8). In this way, from equations (7) and (8), β=γ=α
Therefore, the intermediate frequency in equation (5) and the reference oscillation frequency in equation (6) both change at a rate equal to the rate of change in the input frequency, so that the entire system always operates stably. be.

FIG. 3 shows another embodiment, in which signal components obtained from the input and output ends of the second low-pass filter 154 in FIG. 2 are arbitrarily selected via switch _S1 and filtered into the loop filter. 156 and Johnson counter 158
Instead, a ∠π/2 separator (for example, a frequency divided by 2 ∠π/2 separator, etc.) 158' is used, and its reproduced carrier output is sent to the first and second phase detectors 151, 1.
52 and also to the 1/J frequency divider 122 via a switch _S2 which is interlocked with the switch _S1 , and can operate in the same manner as in FIG.

According to the digital tuning receiver having the PLL synchronous demodulation function as described above,
Since the PLL synchronous demodulation circuit section 15 uses a reference frequency oscillator 20 that also serves as a reference oscillator for the digital tuning section 12, instead of using a dedicated voltage-controlled oscillator as in the past, the configuration is simplified. It can be made cheap. In addition, this corresponds to using a voltage controlled oscillator whose free running frequency is close to an ideal one and whose free running frequency has almost no error with respect to the input frequency. Sensitivity decreases and PLL circuit 15
Even if the gain of the PLL circuit 155 decreases, the lock operation can be performed with the phase error in the regenerated (demodulated) carrier output from the PLL circuit 155 as small as possible, which is much better than before. This can contribute to realizing a highly sensitive receiver.

In other words, when using a dedicated voltage-controlled oscillator as in the past, the oscillation frequency has a wide variation range, so even if the input frequency fluctuates significantly during strong input, it can follow it and perform a lock operation. In general, the input frequency, that is, the stability of the transmission carrier from the broadcasting station is extremely high, so there is a problem that it is not possible to take full advantage of this advantage. In other words, in place of the dedicated voltage-controlled oscillator as described above, even if the reference oscillator 20, which is made of a crystal resonator or the like and has high stability, that is, a very narrow variation range of the oscillation frequency, is used also, there is no problem in practice. Rather, it is better to make it possible to exhibit the advantage of high sensitivity locking characteristics due to the stability of the free-running frequency during weak input.

It goes without saying that the present invention is not limited to the embodiments described above and illustrated, and that various modifications and applications can be made without departing from the gist of the invention.

〔Effect of the invention〕

Therefore, as described in detail above, according to the present invention, an inexpensive and good-quality product can be obtained with the simplest possible configuration.
It becomes possible to provide an improved digital tuning receiver that can add a PLL synchronous demodulation function.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional digital tuning receiver, and FIGS. 2 and 3 are block diagrams showing one embodiment and other embodiments of the digital tuning receiver according to the present invention. DESCRIPTION OF SYMBOLS 11...Mixer, 12...Digital tuning section, 13...Intermediate frequency filter, 14...Intermediate frequency amplifier, 15...PLL synchronous demodulation circuit section, 20...Reference frequency oscillator, 122...1/J frequency divider, 123...
Phase/frequency comparator, 124... Local frequency oscillator, 125... 1/N frequency divider, 151, 152... Phase detector, 153, 154... Low pass filter,
155...PLL circuit, 156...loop filter,
158...Johnson counter, 21...1/M frequency divider, 22...1/K frequency divider.

Claims (1)

[Claims] 1. A digital tuning unit that converts the input signal to be demodulated into a predetermined intermediate frequency signal using the PLL method, and derives an in-phase demodulation output and a quadrature demodulation output from the intermediate frequency signal from this digital tuning unit. , an in-phase carrier for demodulation which is equal to the frequency of the intermediate frequency signal and has a phase difference of 90 degrees from each other by dividing the output from the reference oscillator of the digital tuning section that is controlled based on the orthogonal demodulation output; 1. A digital tuning receiver comprising a PLL synchronous demodulation circuit section that reproduces orthogonal carriers using a PLL method.