JPS6454736A - Manufacture of package - Google Patents

Manufacture of package

Info

Publication number
JPS6454736A
JPS6454736A JP21172187A JP21172187A JPS6454736A JP S6454736 A JPS6454736 A JP S6454736A JP 21172187 A JP21172187 A JP 21172187A JP 21172187 A JP21172187 A JP 21172187A JP S6454736 A JPS6454736 A JP S6454736A
Authority
JP
Japan
Prior art keywords
resin
substrate
mold
semiconductor
molded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21172187A
Other languages
Japanese (ja)
Inventor
Taro Fukui
Shinji Hashimoto
Masaya Tsujimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP21172187A priority Critical patent/JPS6454736A/en
Publication of JPS6454736A publication Critical patent/JPS6454736A/en
Pending legal-status Critical Current

Links

Landscapes

  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

PURPOSE:To mass-produce sealing structure having high moisture resistance by burying a semiconductor element the periphery of which is coated with a resin into a resin in a mold from the surface side of a substrate and molding the element. CONSTITUTION:A semiconductor 2 is loaded onto the surface of a substrate 1, and a conductor circuit 4 is formed onto the surface of the substrate 1. The circuit 4 is connected electrically to an integrated circuit in the element 2 by bonding wires 3 while being electrically connected to lead pins 6. The element 2 on the substrate 1 and the peripheries of the element 2 such as the wire 3 are coated with a resin 7. The whole is turned upside down, and buried into the resin 7 from the surface side of the substrate 1 into the resin 7 admitted into a mold (a formwork) 8 and molded. The whole is molded and removed from the mold, thus acquiring a semiconductor package. Accordingly, sealing structure having high moisture resistance can be mass-produced.
JP21172187A 1987-08-26 1987-08-26 Manufacture of package Pending JPS6454736A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21172187A JPS6454736A (en) 1987-08-26 1987-08-26 Manufacture of package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21172187A JPS6454736A (en) 1987-08-26 1987-08-26 Manufacture of package

Publications (1)

Publication Number Publication Date
JPS6454736A true JPS6454736A (en) 1989-03-02

Family

ID=16610501

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21172187A Pending JPS6454736A (en) 1987-08-26 1987-08-26 Manufacture of package

Country Status (1)

Country Link
JP (1) JPS6454736A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998008251A1 (en) * 1996-08-20 1998-02-26 Hitachi, Ltd. Semiconductor and method for manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998008251A1 (en) * 1996-08-20 1998-02-26 Hitachi, Ltd. Semiconductor and method for manufacturing the same

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