JPS6148952A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6148952A
JPS6148952A JP59170596A JP17059684A JPS6148952A JP S6148952 A JPS6148952 A JP S6148952A JP 59170596 A JP59170596 A JP 59170596A JP 17059684 A JP17059684 A JP 17059684A JP S6148952 A JPS6148952 A JP S6148952A
Authority
JP
Japan
Prior art keywords
insulating substrate
semiconductor pellet
wires
semiconductor device
inner leads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59170596A
Other languages
Japanese (ja)
Inventor
Shiyuuzou Akishima
周三 明島
Seiichi Hirata
誠一 平田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP59170596A priority Critical patent/JPS6148952A/en
Publication of JPS6148952A publication Critical patent/JPS6148952A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To lessen an enclosure even though there are numerous external terminals by a method wherein a semiconductor pellet and inner leads are put on the insulative substrate, wherein numerous fine conductive wires are embedded, and the inner leads are electrically connected with the outside by the fine wires. CONSTITUTION:A semiconductor pellet 1 is put on a bed 2 and the bed 2 is put on an insulative substrate 3. The semiconductor pellet 1 and inner leads 4 are connected using bonding-wires 5. The semiconductor pellet 1, the bed 2, the insulative substrate 3, the inner leads 4 and the bonding-wires 5 are sealed with a molding resin. At this time, the sealing is performed in such a way that the surface on one side of the insulative substrate 3 is exposed. Numerous fine conductive wires 7 are embedded in the insulative substrate 3 and each inner lead is brought into contact electrically to some of the fine conductive wires 7. By this method, the inner leads can be electrically connected with the outside.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は半導体装置、特にモールド樹脂によって封止さ
れた外部端子数の多い半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device, and particularly to a semiconductor device having a large number of external terminals sealed with a molding resin.

〔発明の技術的背景−とその問題点〕[Technical background of the invention and its problems]

従来の半導体装置において、モールド樹脂封止型のもの
は、一般にトランスファモールドによって′Ａ迄される
ため、外部端子が外囲器の周囲に配置されたＤＩＰ型、
ＦＰ型に代表される。しかしながら外部端子数、が増え
、例えば２００　ｐｉｎ以上のものになると、これらの
型のものはその構造上外囲器が非常に大きくなり、また
製造も非常に困難となる。外囲器をできるだけ小さくし
ようどすると、各外部端子間の間隙および端子幅を狭め
ざるを（３ず、各端子の曲がり、接触不良等の問題が生
ずる。In conventional semiconductor devices, mold resin-sealed ones are generally transferred to 'A' by transfer molding.
It is represented by the FP type. However, as the number of external terminals increases, for example to 200 pins or more, these types of devices have very large envelopes due to their structure and are also very difficult to manufacture. If an attempt is made to make the envelope as small as possible, the gaps between the external terminals and the width of the terminals must be narrowed (3), which causes problems such as bending of the terminals and poor contact.

このため、従来、外部端子数の多い半導体装置では、モ
ールド樹脂封止型のものではなく、セラミックパッケー
ジのＰ、Ｇ、Ａ、やデツプキャリアといったものが用い
られている。しかしながらセラミックパッケージの半導
体装置には、製造工程が複雑になり、またコストが高く
なるという欠点がある。For this reason, conventionally, in semiconductor devices having a large number of external terminals, ceramic packages such as P, G, A, and deep carriers have been used instead of molded resin-sealed types. However, ceramic packaged semiconductor devices have the disadvantage that the manufacturing process is complicated and the cost is high.

〔発明の目的〕[Purpose of the invention]

そこで本発明は、外部端子数を多くしても外囲器が大ぎ
くなることがなく、かつ製造が容易であるモールド樹脂
封止型の半導体装置を提供することを目的とする。SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a molded resin-sealed semiconductor device that does not have an oversized envelope even when the number of external terminals is increased and is easy to manufacture.

〔発明の概要〕[Summary of the invention]

本発明の特徴は、モールド樹脂封止型の半導体装置にお
いて、半す体ペレットと、この半導体ペレットにワイヤ
ボンディングされたインナリードとを、導電性の細線を
多ｒｉ埋設した絶縁性基板にのせ、この絶縁性基板の少
なくとも一面が露出し、かつ、前記導電性の細線の一端
が前記露出面から突出し、前記導電性の細線の一部の他
端が前記インナリードに電気的接触するようにモールド
樹ｎａ封止して、外部端子数が多くても外囲器を大きく
する必要をなくし、しかも製造を容易にした点にある。The present invention is characterized in that, in a molded resin-sealed semiconductor device, a half-shaped pellet and an inner lead wire-bonded to the semiconductor pellet are placed on an insulating substrate in which conductive thin wires are buried in a multi-ri manner. The insulating substrate is molded so that at least one surface is exposed, one end of the thin conductive wire protrudes from the exposed surface, and the other end of a portion of the thin conductive wire is in electrical contact with the inner lead. The main advantage is that by sealing the external terminals, there is no need to increase the size of the envelope even if there are a large number of external terminals, and furthermore, manufacturing is facilitated.

〔発明の実施例〕 以下本発明を図示する実施例に基づき説明する。[Embodiments of the invention] The present invention will be described below based on illustrated embodiments.

第１図はこの実施例に係る半導体装置の断面図である。FIG. 1 is a sectional view of a semiconductor device according to this embodiment.

半導体ペレット１はベッド２の上にのせられ、更にベッ
ド２は絶縁性基板３の上にのせられる。半導体ペレット
１とインナリード４とは、従来の方法でボンディングワ
イヤ５により接続される。半導体ベレ”ット１、ベッド
２、絶縁性基板３、インナリード４、ボンディングワイ
ヤ５は、モールド樹脂６によって封止されるが、この際
、絶縁性基板３の一面が露出するようにする。第２図に
絶縁性基板３の部分断面図を示ず、この絶縁性基板３は
導電性の細線７を多数埋設しており、例えば金めつぎし
たステンレスワイヤを埋設したシリコンゴムで形成する
ことができる。また、市販のエラスヂックコネクタをそ
のまま利用することもできる。導電性ＩｌＩ線７は絶縁
性基板の両面かられずかに先端が突出するようにする。The semiconductor pellet 1 is placed on a bed 2, and the bed 2 is further placed on an insulating substrate 3. Semiconductor pellet 1 and inner lead 4 are connected by bonding wire 5 using a conventional method. The semiconductor bellet 1, the bed 2, the insulating substrate 3, the inner leads 4, and the bonding wires 5 are sealed with a molding resin 6, but at this time one surface of the insulating substrate 3 is exposed. A partial cross-sectional view of the insulating substrate 3 is not shown in FIG. 2, and the insulating substrate 3 has a large number of conductive thin wires 7 embedded therein, and may be made of silicone rubber with embedded gold-plated stainless steel wires, for example. It is also possible to use a commercially available elastic connector as is.The ends of the conductive IlI wires 7 should protrude slightly from both sides of the insulating substrate.

第３図は第２図に示す絶縁性基板３の上面図である。導
電性口１２７の直径は１２μｍ程度、埋設間隔は０．３
ｍｍ程度、先端突出部の長さは０．１５ｒＮｎＰｉ！度
にするのが好ましい。FIG. 3 is a top view of the insulating substrate 3 shown in FIG. 2. The diameter of the conductive port 127 is approximately 12 μm, and the buried interval is 0.3 μm.
The length of the tip protrusion is about 0.15rNnPi! It is preferable to do so at a certain degree.

このような構造により、各インナリードは絶縁性基板３
の露出面から突出している導電性細線７のいずれかに電
気的に接触することになり、この導電性細線７を介して
外部と電気的に接続可能となる。実際のプリント基板に
この半導体装置を実装する場合、インナリードの配置に
対応したパターンをプリント基板に作り、この半導体装
置をプリント基板に圧着ずればよい。このとき、実装位
置が多少ずれても、電気的接触に関しては何ら問題がな
い。With this structure, each inner lead is connected to the insulating substrate 3.
It comes into electrical contact with any of the conductive thin wires 7 protruding from the exposed surface of the conductive wire 7, and can be electrically connected to the outside via the conductive thin wires 7. When mounting this semiconductor device on an actual printed circuit board, a pattern corresponding to the arrangement of the inner leads may be created on the printed circuit board, and the semiconductor device may be pressure-bonded to the printed circuit board. At this time, even if the mounting position is slightly shifted, there is no problem with electrical contact.

なお、モールド樹脂封止は従来のトランスファモールド
によって行うことができるが、この際絶縁性基板３とリ
ードフレームとをエポキシ樹脂のような接着剤で仮留め
するのが好ましい。Note that the mold resin sealing can be performed by conventional transfer molding, but in this case, it is preferable to temporarily bond the insulating substrate 3 and the lead frame with an adhesive such as epoxy resin.

〔発明の効果〕〔Effect of the invention〕

以上のとおり本発明によれば、モールド樹脂封止型の半
導体装置において、半導体ペレットと、この半導体ペレ
ットにワイヤボンディングされたインナリードとを、導
電性の細線を多数埋設した絶縁性基板にのせ、この導電
性のｗＪＦＡによってインナリードを外部と電気的に接
続できるようにしたため、外部端子数が多くても外囲器
を大きくする必要はなくなり、しかも製造が容易になる
。As described above, according to the present invention, in a molded resin sealed semiconductor device, a semiconductor pellet and an inner lead wire-bonded to the semiconductor pellet are placed on an insulating substrate in which a large number of conductive thin wires are embedded. Since the inner lead can be electrically connected to the outside using this conductive wJFA, there is no need to increase the size of the envelope even if the number of external terminals is large, and furthermore, manufacturing is facilitated.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明に係る半導体装置の断面図、第２図は第
１図に示す絶縁性基板の拡大図、第３図は第１図に示す
絶縁性基板の上面図である。 １・・・半導体ペレット、２・・・ベッド、３・・・絶
縁性基板、４・・・インナリード、５・・・ボンディン
グヮイＡ７．６・・・モールド樹脂、７・・・導電性の
５ｆｆｌ線。1 is a sectional view of a semiconductor device according to the present invention, FIG. 2 is an enlarged view of the insulating substrate shown in FIG. 1, and FIG. 3 is a top view of the insulating substrate shown in FIG. 1. DESCRIPTION OF SYMBOLS 1... Semiconductor pellet, 2... Bed, 3... Insulating substrate, 4... Inner lead, 5... Bonding wire A7.6... Mold resin, 7... Conductive 5ffl line.

Claims (1)

【特許請求の範囲】 １、半導体ペレットと、この半導体ペレットにワイヤボ
ンディングされたインナリードと、厚み方向に沿つて導
電性の細線を多数埋設した絶縁性基板と、前記半導体ペ
レット、前記インナリード、および前記絶縁性基板を埋
設したモールド樹脂と、を有し、 前記絶縁性基板の少なくとも一面が前記モールド樹脂か
ら露出し、前記導電性の細線の各一端が前記露出面から
突出し、前記導電性の細線の一部の他端が前記インナリ
ードに電気的に接触していることを特徴とする半導体装
置。 ２、絶縁性基板がシリコンゴムから成り、導電性の細線
が金めっきしたステンレスワイヤであることを特徴とす
る特許請求の範囲第１項記載の半導体装置。[Scope of Claims] 1. A semiconductor pellet, an inner lead wire-bonded to the semiconductor pellet, an insulating substrate in which a large number of conductive thin wires are embedded along the thickness direction, the semiconductor pellet, the inner lead, and a molded resin in which the insulating substrate is embedded, at least one surface of the insulating substrate is exposed from the molded resin, one end of each of the conductive thin wires protrudes from the exposed surface, and A semiconductor device characterized in that the other end of a portion of the thin wire is in electrical contact with the inner lead. 2. The semiconductor device according to claim 1, wherein the insulating substrate is made of silicone rubber, and the conductive thin wire is a gold-plated stainless steel wire.
JP59170596A 1984-08-16 1984-08-16 Semiconductor device Pending JPS6148952A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59170596A JPS6148952A (en) 1984-08-16 1984-08-16 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59170596A JPS6148952A (en) 1984-08-16 1984-08-16 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6148952A true JPS6148952A (en) 1986-03-10

Family

ID=15907768

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59170596A Pending JPS6148952A (en) 1984-08-16 1984-08-16 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6148952A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0368262A2 (en) * 1988-11-09 1990-05-16 Nitto Denko Corporation Wiring substrate, film carrier, semiconductor device made by using the film carrier, and mounting structure comprising the semiconductor device
EP0811245A1 (en) * 1995-09-27 1997-12-10 Texas Instruments Incorporated Microelectronic assemblies including z-axis conductive films
US5808357A (en) * 1992-06-02 1998-09-15 Fujitsu Limited Semiconductor device having resin encapsulated package structure
EP0875936A3 (en) * 1997-05-02 1999-05-26 Shinko Electric Industries Co. Ltd. Wiring substrate having vias

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0368262A2 (en) * 1988-11-09 1990-05-16 Nitto Denko Corporation Wiring substrate, film carrier, semiconductor device made by using the film carrier, and mounting structure comprising the semiconductor device
US5072289A (en) * 1988-11-09 1991-12-10 Nitto Denko Corporation Wiring substrate, film carrier, semiconductor device made by using the film carrier, and mounting structure comprising the semiconductor device
US5808357A (en) * 1992-06-02 1998-09-15 Fujitsu Limited Semiconductor device having resin encapsulated package structure
US6031280A (en) * 1992-06-02 2000-02-29 Fujitsu Limited Semiconductor device having resin encapsulated package structure
US6271583B1 (en) 1992-06-02 2001-08-07 Fujitsu Limited Semiconductor device having resin encapsulated package structure
EP0811245A1 (en) * 1995-09-27 1997-12-10 Texas Instruments Incorporated Microelectronic assemblies including z-axis conductive films
EP0811245A4 (en) * 1995-09-27 1998-11-18 Texas Instruments Inc Microelectronic assemblies including z-axis conductive films
EP0875936A3 (en) * 1997-05-02 1999-05-26 Shinko Electric Industries Co. Ltd. Wiring substrate having vias
US6093476A (en) * 1997-05-02 2000-07-25 Shinko Electric Industries Co., Ltd. Wiring substrate having vias
KR100285113B1 (en) * 1997-05-02 2001-06-01 모기 쥰이찌 Wiring board

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