JPS6454133U - - Google Patents

Description

[Brief explanation of drawings]

Fig. 1 is a block diagram of a microcomputer circuit showing an embodiment of the present invention, Fig. 2 is a block diagram of a conventional microcomputer circuit, and Fig. 3 is a low power shottsky transistor/transistor logic type integrated circuit ( LS-TTLIC)
and complementary metal oxide semiconductor type integrated circuits (C-
FIG. 4 is a graph showing power consumption characteristics with MOSIC). 1...Clock circuit, 2...Central processing unit (CPU
), 3... Read-only memory (ROM), 4... Input/output port (I/O port), 5... Clock signal line, 6... Address bus, 7... Data bus, 8... Control bus, 9... Clock switching circuit, 1
0...Clock switching signal line, 11...Peripheral device requiring high-speed control, 12...Low-speed peripheral device consuming large power, 13...High-speed control signal line, 14...Low-speed control signal line.

Claims (1)

[Claims for Utility Model Registration] In a microcomputer circuit to which various peripheral devices having different operating speeds are connected, a microcomputer circuit that adapts to the operating speed of the peripheral device in accordance with a program for operating the peripheral device. a storage means that stores in advance the frequency of the operating basic clock signal; and a switching means that reads the frequency from the storage means when the program is executed and switches the clock signal to this frequency, and the clock signal is switched by the switching means. A microcomputer circuit characterized in that it is operated by a clock signal.