JPS59157895A - Integrated circuit device incorporating read-only memory - Google Patents
Integrated circuit device incorporating read-only memoryInfo
- Publication number
- JPS59157895A JPS59157895A JP58032283A JP3228383A JPS59157895A JP S59157895 A JPS59157895 A JP S59157895A JP 58032283 A JP58032283 A JP 58032283A JP 3228383 A JP3228383 A JP 3228383A JP S59157895 A JPS59157895 A JP S59157895A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- circuit device
- memory
- internal clock
- prom
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000013078 crystal Substances 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
Landscapes
- Read Only Memory (AREA)
- Semiconductor Memories (AREA)
- Power Sources (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、集積回路装置に関し、特に相補型絶縁ゲート
電界効果トランジスタ(0MO8)のプログラマブルリ
ードオンリーメモリ(FROM)又は0MO8のFRO
M内蔵のプロセッサユニッ)(CPU)に適用し得る集
積回路の構成に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to integrated circuit devices, and in particular to complementary insulated gate field effect transistors (0MO8) programmable read only memory (FROM) or 0MO8 FRO
The present invention relates to the configuration of an integrated circuit that can be applied to a processor unit (CPU) with a built-in CPU.
従来、この種のFROMもしくは、FROM内蔵の集積
回路はFROMにデータを書込む際P ROM部以外に
もクロックが供給されており、そのため、回路はある状
態で動作をしてた。したがってこの状態では電力はかな
り消費される欠点がある。Conventionally, in this type of FROM or an integrated circuit with a built-in FROM, a clock was supplied to a part other than the PROM section when writing data to the FROM, and therefore the circuit operated in a certain state. Therefore, this state has the disadvantage that a considerable amount of power is consumed.
本発明は、書込信号で内部のクロックを停止させること
によシ上記欠点を無くし、書込中には電力の消費を極力
少なくするようにした装置を提供するものである。The present invention eliminates the above drawbacks by stopping the internal clock with a write signal, and provides a device that consumes as little power as possible during writing.
これによシ、PRO,M内蔵のIchip CMO8集
積回路において書込信号とこの畳込信号で制御されるシ
ステムクロック?有することを特徴とした集積回路装置
が得られる。Accordingly, the system clock controlled by the write signal and this convolution signal in the Ichip CMO8 integrated circuit with built-in PRO,M? An integrated circuit device characterized by having the following features is obtained.
次に本発明の実施例について図面を参照して説明する。Next, embodiments of the present invention will be described with reference to the drawings.
第1図は外部クリスタルでクロックを発生させるもので
、穎込信゛号1がHighレベルになるとPROM部は
書込動作に入るが、FROM以外へは、書込信号1によ
υ制御ゲート5がOFF状態になり、内部クロック6は
回路内部へは送られない。そのため各回路のゲートはス
イッチングが起らず消費電力が少なくなる。In FIG. 1, the clock is generated by an external crystal. When the write signal 1 becomes high level, the PROM section starts the write operation, but the write signal 1 causes the υ control gate 5 to is turned off, and the internal clock 6 is not sent inside the circuit. Therefore, no switching occurs at the gates of each circuit, reducing power consumption.
第2図は、他の実施例全庁し外部からのクロッり入力9
が制御グー)11に入シ回路内部へ内部クロック10と
して送られるが、同様に書込信号7によシ制御ゲート1
1がOFFとなシ内部クロック10はLOWレベルの状
態で止る。このようにして、PROM8VCは誉込互れ
るが、その間PROM以外の所の回路消質電力は少なく
なる。FIG. 2 shows another embodiment in which clock input from the outside is 9.
is sent to the control gate 11 as an internal clock 10 to the inside of the control gate 11.
1 is OFF, the internal clock 10 remains at a LOW level. In this way, the PROM8VC is regenerated, but in the meantime, the power dissipated in circuits other than the PROM is reduced.
コ(7)ように、FROM内蔵の1chip CMO
8集積回路ycPROM部への書込信号を内部クロック
の制御用として使うだけで、書込に対する効果は変らな
いが、PROM以外で消費される電力を極力少なくした
集積回路装置が帰られるわけである。1chip CMO with built-in FROM as shown in (7)
8 By simply using the write signal to the ycPROM part of the integrated circuit to control the internal clock, the effect on writing remains the same, but an integrated circuit device can be created that consumes as little power as possible in areas other than the PROM. .
第1図は、本発明の一実施例全部分的にブロックで示し
た回路図、第2図は他の実施例を部分的にブロックで示
した回路図である。
なお図において、l・・・・・・書込信号、2・・・・
・・PROM部、3・・・・・・C,G、部、 4・・
・・・・外部クリスタル、5・・・・・・制御ゲート、
6・・・・・・内部クロック、7・・・・・・書込信号
、8・・・・・・PROM部、9・・・・・・クロック
入力、10・・・・・・内部クロック、11・・・・・
・制御ゲート、である。FIG. 1 is a circuit diagram showing one embodiment of the present invention partially in blocks, and FIG. 2 is a circuit diagram partially showing another embodiment in blocks. In the figure, l... write signal, 2...
...PROM part, 3...C, G, part, 4...
...External crystal, 5...Control gate,
6... Internal clock, 7... Write signal, 8... PROM section, 9... Clock input, 10... Internal clock , 11...
- Control gate.
Claims (1)
、書込信号と、該書込信号で制御されるシステムクロッ
クとを有することを特徴とするリードオンリーメモリを
内蔵する集積回路装置。An integrated circuit device having a built-in read-only memory, the integrated circuit device having a built-in read-only memory, the integrated circuit device having a write signal and a system clock controlled by the write signal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58032283A JPS59157895A (en) | 1983-02-28 | 1983-02-28 | Integrated circuit device incorporating read-only memory |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58032283A JPS59157895A (en) | 1983-02-28 | 1983-02-28 | Integrated circuit device incorporating read-only memory |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS59157895A true JPS59157895A (en) | 1984-09-07 |
Family
ID=12354639
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58032283A Pending JPS59157895A (en) | 1983-02-28 | 1983-02-28 | Integrated circuit device incorporating read-only memory |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59157895A (en) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5368051A (en) * | 1976-11-29 | 1978-06-17 | Sharp Corp | Integrated circuit device |
JPS5449037A (en) * | 1977-09-27 | 1979-04-18 | Fujitsu Ltd | Timing contol system of memory unit |
JPS5753299B2 (en) * | 1976-01-16 | 1982-11-12 |
-
1983
- 1983-02-28 JP JP58032283A patent/JPS59157895A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5753299B2 (en) * | 1976-01-16 | 1982-11-12 | ||
JPS5368051A (en) * | 1976-11-29 | 1978-06-17 | Sharp Corp | Integrated circuit device |
JPS5449037A (en) * | 1977-09-27 | 1979-04-18 | Fujitsu Ltd | Timing contol system of memory unit |
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