JPS6449340A - Transmitting path encoding circuit - Google Patents
Transmitting path encoding circuitInfo
- Publication number
- JPS6449340A JPS6449340A JP20568987A JP20568987A JPS6449340A JP S6449340 A JPS6449340 A JP S6449340A JP 20568987 A JP20568987 A JP 20568987A JP 20568987 A JP20568987 A JP 20568987A JP S6449340 A JPS6449340 A JP S6449340A
- Authority
- JP
- Japan
- Prior art keywords
- data
- code
- inputted
- error correcting
- error
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
PURPOSE:To ease clock extraction and to eliminate a PLL for speed conversion by causing the number of bits, which is at a time an error correcting code, a frame detecting code and other data are multiplexed, to be the two-fold of data to be transmitted and inverting one bit of the error correcting code, at least. CONSTITUTION:Data MO, which are successively inputted, are compressed to intermittent data with causing a timing slot to be half. The compressed data DS are inputted to an error detecting code preparing circuit. While the data are inputted, a switch 11 is turned on. When there is no data DS, the switch 11 is turned off and the error correcting code is outputted during this. A selector 10 executes the switching of the DS, a C and an F and composes a transmitting code. At such a time, a CO is inverted in a code inverting circuit 9 and outputted and a '0' succession and a '1' succession are eliminated. Then, the clock extraction is eased in a receiving side. Thus, since an error correction is possible, the data transmission of high quality can be executed even when a number of transmitting path errors are generated.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20568987A JPS6449340A (en) | 1987-08-19 | 1987-08-19 | Transmitting path encoding circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20568987A JPS6449340A (en) | 1987-08-19 | 1987-08-19 | Transmitting path encoding circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6449340A true JPS6449340A (en) | 1989-02-23 |
Family
ID=16511077
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP20568987A Pending JPS6449340A (en) | 1987-08-19 | 1987-08-19 | Transmitting path encoding circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6449340A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPWO2011068045A1 (en) * | 2009-12-01 | 2013-04-18 | 三菱電機株式会社 | Error correction method and apparatus |
-
1987
- 1987-08-19 JP JP20568987A patent/JPS6449340A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPWO2011068045A1 (en) * | 2009-12-01 | 2013-04-18 | 三菱電機株式会社 | Error correction method and apparatus |
JP5566400B2 (en) * | 2009-12-01 | 2014-08-06 | 三菱電機株式会社 | Error correction method and apparatus |
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