JPS6447118A - Minimum pulse width check circuit - Google Patents

Minimum pulse width check circuit

Info

Publication number
JPS6447118A
JPS6447118A JP62203155A JP20315587A JPS6447118A JP S6447118 A JPS6447118 A JP S6447118A JP 62203155 A JP62203155 A JP 62203155A JP 20315587 A JP20315587 A JP 20315587A JP S6447118 A JPS6447118 A JP S6447118A
Authority
JP
Japan
Prior art keywords
pulse
test
clock
pulse width
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62203155A
Other languages
Japanese (ja)
Inventor
Hiroyuki Yasuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62203155A priority Critical patent/JPS6447118A/en
Publication of JPS6447118A publication Critical patent/JPS6447118A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To detect a defective FF by inputting a test pulse for setting or resetting the FF and varying the phase of the pulse and that of a clock pulse so as to form the contention state and comparing the result with that of a nondefective FF. CONSTITUTION:In inputting a pulse to a clock terminal CLK and a test input terminal RSET 0, a test pulse is given from an output Q of the FF 2 to a FF 1, which is reset. The phase of the clock pulse of the FF 1 and that of the test pulse are varied from this state to form the state where the clock pulse and the test pulse is in contention. Then a check pattern of the output of a nondefective FF when the test pulse is inputted thereto is formed and the pattern is compared with a pattern of the output Q of an FF being an object of inspection. Thus, FFs whose minimum pulse width for setting or resetting is deteriorated are detected and they can be excluded.
JP62203155A 1987-08-17 1987-08-17 Minimum pulse width check circuit Pending JPS6447118A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62203155A JPS6447118A (en) 1987-08-17 1987-08-17 Minimum pulse width check circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62203155A JPS6447118A (en) 1987-08-17 1987-08-17 Minimum pulse width check circuit

Publications (1)

Publication Number Publication Date
JPS6447118A true JPS6447118A (en) 1989-02-21

Family

ID=16469341

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62203155A Pending JPS6447118A (en) 1987-08-17 1987-08-17 Minimum pulse width check circuit

Country Status (1)

Country Link
JP (1) JPS6447118A (en)

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