JPS6447038A - Junction structure - Google Patents

Junction structure

Info

Publication number
JPS6447038A
JPS6447038A JP62203553A JP20355387A JPS6447038A JP S6447038 A JPS6447038 A JP S6447038A JP 62203553 A JP62203553 A JP 62203553A JP 20355387 A JP20355387 A JP 20355387A JP S6447038 A JPS6447038 A JP S6447038A
Authority
JP
Japan
Prior art keywords
lead
electrode terminal
junctioning
alloy
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62203553A
Other languages
Japanese (ja)
Inventor
Osamu Osada
Hirotaka Nakano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP62203553A priority Critical patent/JPS6447038A/en
Publication of JPS6447038A publication Critical patent/JPS6447038A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To realize a reliable bondage at low temperature and under low pressure by a method wherein a junction, consisting of a lead attached to an insulating film and an electrode terminal of an electronic part, is bonded to the electrode terminal and an insulating body in its vicinity. CONSTITUTION:The surface of a lead 14 built of a film carrier junctioning alloy is subjected to etching in diluted hydrochloric acid, washing, and natural dry out. An electrode terminal 31 of an integrated circuit element 30 is aligned with the end of the lead 14. The lead 14, the electrode terminal 31, and a passivation film 32 in their vicinity are subjected to thermal contact bonding. In a connecting process, a heater is allowed to rise to 150 deg.C where it is switched off, but pressure is kept on until the temperature is as low as 134 deg.C that is the melting point of the junctioning alloy, after which a bonding tool 40 is removed. A film carrier inner lead is heated for the simultaneous accomplishment of plastic deformation of the junctioning alloy and the thermal contact bonding of the lead 14, the electrode terminal 31, and the passivation film 32 protecting their neighborhood.
JP62203553A 1987-08-18 1987-08-18 Junction structure Pending JPS6447038A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62203553A JPS6447038A (en) 1987-08-18 1987-08-18 Junction structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62203553A JPS6447038A (en) 1987-08-18 1987-08-18 Junction structure

Publications (1)

Publication Number Publication Date
JPS6447038A true JPS6447038A (en) 1989-02-21

Family

ID=16476043

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62203553A Pending JPS6447038A (en) 1987-08-18 1987-08-18 Junction structure

Country Status (1)

Country Link
JP (1) JPS6447038A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5518957A (en) * 1991-10-10 1996-05-21 Samsung Electronics Co., Ltd. Method for making a thin profile semiconductor package
US5686352A (en) * 1993-07-26 1997-11-11 Motorola Inc. Method for making a tab semiconductor device with self-aligning cavity and intrinsic standoff
US5849607A (en) * 1993-11-27 1998-12-15 Samsung Electronics Co., Ltd. Process for attaching a lead frame to a semiconductor chip

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5518957A (en) * 1991-10-10 1996-05-21 Samsung Electronics Co., Ltd. Method for making a thin profile semiconductor package
US5686352A (en) * 1993-07-26 1997-11-11 Motorola Inc. Method for making a tab semiconductor device with self-aligning cavity and intrinsic standoff
US5849607A (en) * 1993-11-27 1998-12-15 Samsung Electronics Co., Ltd. Process for attaching a lead frame to a semiconductor chip

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