JPS6446963A - Package for semiconductor integrated circuit - Google Patents

Package for semiconductor integrated circuit

Info

Publication number
JPS6446963A
JPS6446963A JP62204702A JP20470287A JPS6446963A JP S6446963 A JPS6446963 A JP S6446963A JP 62204702 A JP62204702 A JP 62204702A JP 20470287 A JP20470287 A JP 20470287A JP S6446963 A JPS6446963 A JP S6446963A
Authority
JP
Japan
Prior art keywords
pattern
integrated circuit
semiconductor integrated
check
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62204702A
Other languages
Japanese (ja)
Other versions
JPH0714022B2 (en
Inventor
Mutsuo Saito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62204702A priority Critical patent/JPH0714022B2/en
Publication of JPS6446963A publication Critical patent/JPS6446963A/en
Publication of JPH0714022B2 publication Critical patent/JPH0714022B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To enable easily the failure obstacle analysis of a semiconductor integrated circuit after cap sealing, from the outside, by arranging exposed check-pattern-measuring-terminals outside a forming region of external connection lead if a package for a semiconductor integrated circuit. CONSTITUTION:A plurality of metallized patterns 7 for check pattern are formed, on the edge portions of four sides of outer peripheral part on the mounting surface of semiconductor integrated circuit of a substrate 1a except the forming region of a metallized pattern 9 on the substrate 1a. A plurality of exposed check-pattern measuring-terminals 8 are formed in the recessed parts arranged on the outer peripheral part of the bottom part of the substrate 1a. Each of the metallized patterns 7 and each of the check pattern- measuringterminals 8 are connected via a through hole 10 so as to correspond with each other. By using the exposed check-pattern-measuringterminals 8, a check pattern formed on the semiconductor integrated circuit in which basic elements such as a transistor and a resistor and the similar ones are patternized, can be measured from the outside.
JP62204702A 1987-08-17 1987-08-17 Package for semiconductor integrated circuit Expired - Lifetime JPH0714022B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62204702A JPH0714022B2 (en) 1987-08-17 1987-08-17 Package for semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62204702A JPH0714022B2 (en) 1987-08-17 1987-08-17 Package for semiconductor integrated circuit

Publications (2)

Publication Number Publication Date
JPS6446963A true JPS6446963A (en) 1989-02-21
JPH0714022B2 JPH0714022B2 (en) 1995-02-15

Family

ID=16494897

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62204702A Expired - Lifetime JPH0714022B2 (en) 1987-08-17 1987-08-17 Package for semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPH0714022B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6010915A (en) * 1995-10-31 2000-01-04 Hewlett-Packard Company High performance debug I/O
JP2008034541A (en) * 2006-07-27 2008-02-14 Kyocera Corp Electronic component housing package, multi-piece production electronic component housing package, and electronic apparatus

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6010915A (en) * 1995-10-31 2000-01-04 Hewlett-Packard Company High performance debug I/O
JP2008034541A (en) * 2006-07-27 2008-02-14 Kyocera Corp Electronic component housing package, multi-piece production electronic component housing package, and electronic apparatus

Also Published As

Publication number Publication date
JPH0714022B2 (en) 1995-02-15

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