JPH037954Y2 - - Google Patents
Info
- Publication number
- JPH037954Y2 JPH037954Y2 JP1984051590U JP5159084U JPH037954Y2 JP H037954 Y2 JPH037954 Y2 JP H037954Y2 JP 1984051590 U JP1984051590 U JP 1984051590U JP 5159084 U JP5159084 U JP 5159084U JP H037954 Y2 JPH037954 Y2 JP H037954Y2
- Authority
- JP
- Japan
- Prior art keywords
- package
- evaluation
- integrated circuit
- rom
- circuit device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000011156 evaluation Methods 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 2
- 101001046426 Homo sapiens cGMP-dependent protein kinase 1 Proteins 0.000 description 10
- 102100022422 cGMP-dependent protein kinase 1 Human genes 0.000 description 10
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000011990 functional testing Methods 0.000 description 2
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【考案の詳細な説明】
本考案は、ワンチツプ・マイクロコンピユータ
等の集積回路素子が封入されてなる集積回路装置
に係り、特にワンチツプ・マイクロコンピユータ
の機能の評価が行なえるようなICパツケージに
関するものである。[Detailed description of the invention] The present invention relates to an integrated circuit device such as a one-chip microcomputer in which integrated circuit elements are enclosed, and in particular relates to an IC package that can evaluate the functions of a one-chip microcomputer. be.
最近のワンチツプ・マイコンでは、内蔵される
ROM,PLA及び入出力ポート等がユーザにより
選択できるようマスクオプシヨンになつている。
そのため、ワンチツプ・マイコンでは、実際の量
産に入る前に、マスクオプシヨンはなされていな
いが完成品とほぼ同一の評価用のチツプを製造し
ておいて、マスクオプシヨンになつている機能に
ついてはその部分の代りとなる所定の回路を外付
かして、各種ワンチツプ・マイコンの機能試験を
行なつて評価する必要がある。また、ユーザプロ
グラム等が書き込まれているROMについては、
通常マスクROMで形成されるが、少量生産品な
どでは上記評価時にプログラムのデバツグが行な
えるようEPROMとして内蔵することもある。 In recent one-chip microcontrollers, the built-in
The ROM, PLA, input/output ports, etc. are mask options that can be selected by the user.
Therefore, for one-chip microcontrollers, before going into actual mass production, we manufacture an evaluation chip that is almost the same as the finished product but does not have mask options. It is necessary to externally attach a predetermined circuit to replace the one-chip microcontroller, and perform functional tests and evaluations on various one-chip microcomputers. Also, regarding the ROM in which user programs etc. are written,
It is usually formed with a mask ROM, but in small-volume production products, it may be built in as an EPROM so that program debugging can be performed during the above evaluation.
上記のようにして評価するためには、外付けす
る場合は外付け用の外部端子等の導通手段が本来
ICパツケージに配列されている正規の外部端子
以外に設けておく必要があり、またEPROMを内
蔵する場合も、それへの書込みのための導通手段
が必要である。 In order to evaluate as described above, if it is externally connected, it is necessary that the conduction means such as the external terminal for external
It is necessary to provide a terminal other than the regular external terminals arranged on the IC package, and even if an EPROM is built-in, a conduction means is required for writing to it.
そこで本考案は上記問題点を解決するために、
基板表面に回路を集積したマイクロコンピユータ
素子がICパツケージに封入されてなる集積回路
装置において、該ICパツケージの下部に規格通
りに配列された正規の外部端子と、該ICパツケ
ージの上部に、該マイクロコンピユータ素子の機
能評価時に他のICパツケージが搭載できるよう
配列された外部端子の受け孔よりなる評価用導通
手段を設けたことを特徴とする集積回路装置を提
供するものです。 Therefore, in order to solve the above problems, this invention
In an integrated circuit device in which a microcomputer element with a circuit integrated on the surface of the substrate is enclosed in an IC package, regular external terminals are arranged according to the standard at the bottom of the IC package, and the microcomputer element is placed at the top of the IC package. The present invention provides an integrated circuit device characterized in that it is equipped with evaluation conduction means consisting of external terminal receiving holes arranged so that other IC packages can be mounted during functional evaluation of computer elements.
以下別途出願の例並びに本考案の一実施例を図
面に従つて詳細に説明する。 Hereinafter, an example of a separate application and an embodiment of the present invention will be described in detail with reference to the drawings.
第1図及び第2図は別途出願の例である集積回
路装置の平面図及び側面図である。 1 and 2 are a plan view and a side view of an integrated circuit device, which is an example of a separately filed application.
本例はワンチツプ・マイコン等の素子(図示せ
ず)を収容した42ピンのICパツケージPKGで、
42本の正規の外部端子RLがその形状や位置(例
えば第2図中のl)等が規格通りに配列されてい
て、さらに素子の機能評価時に利用される評価用
外部端子ELが別途設けられている。このような
装置に評価用の素子を収容し、マザーボード等に
実装し、さらに評価用の外部端子ELを介して所
定の模擬のROM,PLA、入出力ポート等の回路
を実装して、各種の機能試験を行なう。 This example is a 42-pin IC package PKG that houses elements such as a one-chip microcontroller (not shown).
The 42 regular external terminals RL are arranged according to the standard in terms of shape and position (for example, l in Figure 2), and a separate evaluation external terminal EL is provided to be used when evaluating the functionality of the device. ing. A device for evaluation is housed in such a device, mounted on a motherboard, etc., and circuits such as a predetermined simulated ROM, PLA, input/output port, etc. are mounted via the external terminal EL for evaluation, and various types of Perform a functional test.
そして、上記の評価終了後、今度は完成した素
子を収容して、実際に集積回路装置として使用す
るが、その時は、例えば評価用外部端子ELを切
断してマザーボードに実載するようにする。その
際、正規の外部端子RLは規格通りに配列されて
いるので何ら支障はない。 After the above evaluation is completed, the completed device is then housed and actually used as an integrated circuit device. At that time, for example, the external evaluation terminal EL is cut off and the device is mounted on the motherboard. In this case, there will be no problem since the regular external terminals RL are arranged according to the standard.
第3図及び第4図は本考案の一実施例の平面図
及び側面図である。本実施例では、ICパツケー
ジRKG上部に他のICパツケージPKG1が搭載で
きるよう、ICパツケージPKG上面に外部端子の
受け孔EHが配列されている。収容される素子と
受け孔EHとの導通はICパツケージPKGの積層時
の多層配線により行なつている。そしてICパツ
ケージPKGには正規の外部端子RLが前述の別途
出願の例と同様に規格通り配列されている。本実
施例で評価時に搭載される他のICパツケージ
PKG1としては、例えばROM等が考えられる。
つまり、評価時においては搭載されたROMがワ
ンチツプ・マイコンに内蔵されるROMの代りに
利用され、完成された素子が収容されればROM
は搭載されない。 3 and 4 are a plan view and a side view of an embodiment of the present invention. In this embodiment, external terminal receiving holes EH are arranged on the top surface of the IC package RKG so that another IC package PKG1 can be mounted on the top of the IC package RKG. Electrical conduction between the accommodated element and the receiving hole EH is achieved by multilayer wiring when the IC package PKG is laminated. In the IC package PKG, regular external terminals RL are arranged according to the standard, similar to the above-mentioned example of the separate application. Other IC packages installed during evaluation in this example
As PKG1, for example, ROM etc. can be considered.
In other words, during evaluation, the installed ROM is used in place of the ROM built into the one-chip microcontroller, and once the completed device is accommodated, the ROM is
is not installed.
本考案で重要な点は、評価用の素子を収容する
にしろ、完成された素子を収容するにしろ、いず
れの場合も同じICパツケージが利用できるとい
う点である。そのために正規の外部端子RLは、
規格通りに配列されている。 An important point of the present invention is that the same IC package can be used whether it is accommodating an element for evaluation or a completed element. For that purpose, the regular external terminal RL is
Arranged according to standards.
本考案によれば、評価時に使用するROM等の
ICパツケージPKG1がICパツケージPKGに簡単
に接続、実装でき、またICパツケージPKG,
PKG1を実装する実装基板に対して高密度にIC
パツケージの実装ができる。 According to the present invention, the ROM, etc. used during evaluation
IC package PKG1 can be easily connected and mounted to IC package PKG.
IC is placed in high density on the mounting board on which PKG1 is mounted.
Packages can be implemented.
本考案のようにすれば、特に少量生産品の場
合、評価時のICパツケージ、マザーボード等が
完成品の場合と同じものが利用できるので、価格
の面で非常に有効である。 The present invention is very effective in terms of cost, especially in the case of products produced in small quantities, since the same IC package, motherboard, etc. can be used during evaluation as in the case of the finished product.
第1図、第2図は別途出願の一例の平面図、側
面図、第3図、第4図は本考案の一実施例の平面
図、側面図である。
図中、PKG;ICパツケージ、PKG1;他のIC
パツケージ、RL;正規の外部端子、EL;評価用
の外部端子、EH;外部端子の受け孔。
1 and 2 are a plan view and a side view of an example of the separately filed application, and FIGS. 3 and 4 are a plan view and a side view of an embodiment of the present invention. In the figure, PKG: IC package, PKG1: other IC
Package cage, RL: Regular external terminal, EL: External terminal for evaluation, EH: External terminal receiving hole.
Claims (1)
タ素子がICパツケージに封入されてなる集積回
路装置において、 該ICパツケージの下部に規格通りに配列され
た正規の外部端子と、 該ICパツケージの上部に、該マイクロコンピ
ユータ素子の機能評価時に他のICパツケージが
搭載できるよう配列された外部端子の受け孔より
なる評価用導通手段を設けたことを特徴とする集
積回路装置。[Claim for Utility Model Registration] An integrated circuit device in which a microcomputer element with circuits integrated on the surface of a substrate is enclosed in an IC package, including regular external terminals arranged according to standards at the bottom of the IC package; 1. An integrated circuit device, characterized in that an evaluation conduction means is provided on the upper part of the IC package, the conduction means consisting of receiving holes for external terminals arranged so that another IC package can be mounted when evaluating the function of the microcomputer element.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5159084U JPS6039253U (en) | 1984-04-09 | 1984-04-09 | integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5159084U JPS6039253U (en) | 1984-04-09 | 1984-04-09 | integrated circuit device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6039253U JPS6039253U (en) | 1985-03-19 |
JPH037954Y2 true JPH037954Y2 (en) | 1991-02-27 |
Family
ID=30181998
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5159084U Granted JPS6039253U (en) | 1984-04-09 | 1984-04-09 | integrated circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6039253U (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5731847B2 (en) * | 1974-06-11 | 1982-07-07 |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS645889Y2 (en) * | 1980-07-31 | 1989-02-14 |
-
1984
- 1984-04-09 JP JP5159084U patent/JPS6039253U/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5731847B2 (en) * | 1974-06-11 | 1982-07-07 |
Also Published As
Publication number | Publication date |
---|---|
JPS6039253U (en) | 1985-03-19 |
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