KR910008828A - Semiconductor Device Package - Google Patents

Semiconductor Device Package Download PDF

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Publication number
KR910008828A
KR910008828A KR1019900015305A KR900015305A KR910008828A KR 910008828 A KR910008828 A KR 910008828A KR 1019900015305 A KR1019900015305 A KR 1019900015305A KR 900015305 A KR900015305 A KR 900015305A KR 910008828 A KR910008828 A KR 910008828A
Authority
KR
South Korea
Prior art keywords
film substrate
semiconductor device
device package
sides
lead patterns
Prior art date
Application number
KR1019900015305A
Other languages
Korean (ko)
Other versions
KR940003374B1 (en
Inventor
유따까 마끼노
Original Assignee
다니이 아끼오
마쯔시다덴기산교 가부시기가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 다니이 아끼오, 마쯔시다덴기산교 가부시기가이샤 filed Critical 다니이 아끼오
Publication of KR910008828A publication Critical patent/KR910008828A/en
Application granted granted Critical
Publication of KR940003374B1 publication Critical patent/KR940003374B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

내용 없음No content

Description

반도체소자패키지Semiconductor Device Package

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제 1 도는 본 발명의 실시예를 표시한 실장상태의 단면도1 is a cross-sectional view of a mounting state showing an embodiment of the present invention.

제 2 도는 바닥면쪽의 리이드패턴을 표시한 평면도2 is a plan view showing the lead pattern on the bottom side

제 3 도는 위면쪽의 리이드패턴을 표시한 평면도.3 is a plan view showing the lead pattern on the upper side.

Claims (1)

필름기판의 양면에 각각 반도체소자가 탑재되어서, 이들 반도체소자의 각 전극이, 필름기판의 양면에 각각 형성된 리이드패턴에 접속되고, 적어도 일부의 리이드 패턴이, 필름기판을 관통하는 관통구멍에 의해서, 필름기판의 한쪽면으로부터 다른쪽면으로 접속되어 있는 동시에 필름기판양면의 각 반도체소자가 봉지수지로 일체적으로 봉입되어 있는 것을 특징으로 하는 반도체소자패키지.Semiconductor elements are mounted on both sides of the film substrate so that each electrode of these semiconductor elements is connected to lead patterns formed on both sides of the film substrate, and at least some of the lead patterns are formed by through holes penetrating the film substrate. A semiconductor device package which is connected from one side of a film substrate to the other side, and each semiconductor element on both sides of the film substrate is integrally encapsulated with a sealing resin. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900015305A 1989-10-03 1990-09-26 Package of semiconductor device KR940003374B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP1-259202 1989-10-03
JP1259202A JP2734684B2 (en) 1989-10-03 1989-10-03 Semiconductor device package

Publications (2)

Publication Number Publication Date
KR910008828A true KR910008828A (en) 1991-05-31
KR940003374B1 KR940003374B1 (en) 1994-04-21

Family

ID=17330806

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900015305A KR940003374B1 (en) 1989-10-03 1990-09-26 Package of semiconductor device

Country Status (2)

Country Link
JP (1) JP2734684B2 (en)
KR (1) KR940003374B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4865197B2 (en) 2004-06-30 2012-02-01 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof

Also Published As

Publication number Publication date
JP2734684B2 (en) 1998-04-02
JPH03120749A (en) 1991-05-22
KR940003374B1 (en) 1994-04-21

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