JPS6446951A - Master slice system semiconductor integrated circuit - Google Patents

Master slice system semiconductor integrated circuit

Info

Publication number
JPS6446951A
JPS6446951A JP20470187A JP20470187A JPS6446951A JP S6446951 A JPS6446951 A JP S6446951A JP 20470187 A JP20470187 A JP 20470187A JP 20470187 A JP20470187 A JP 20470187A JP S6446951 A JPS6446951 A JP S6446951A
Authority
JP
Japan
Prior art keywords
wiring
clamping
region
clamp
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP20470187A
Other languages
Japanese (ja)
Other versions
JPH0646653B2 (en
Inventor
Sadaji Tasai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP20470187A priority Critical patent/JPH0646653B2/en
Publication of JPS6446951A publication Critical patent/JPS6446951A/en
Publication of JPH0646653B2 publication Critical patent/JPH0646653B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits

Abstract

PURPOSE:To reduce the wiring for clamping in a wiring region to the utmost, and exclude an obstacle to the connection of general signals in automatic wiring design, by providing a common clamping signal wiring for clamping voltage which is independent of individual type pattern. CONSTITUTION:A clamping signal wiring 106 is one in which a wiring to clamp a logic value '1' is arranged in a wiring region 105 between logic cell raws 104, as a common pattern independent of types. Therefore, gate groups 108 requiring to clamp the logic value '1' can obtain a specified input voltage by connecting their inputs to the clamping signal wiring 106, and signal wirings for that purpose can be reduced to a minimum. Further, by arranging a clamping voltage generating circuit outside the cell raw region, cells for clamping which are arranged everywhere in the prior art are unnecessitated. Thereby, at the time of performing an automatic wiring design applying a computer, the connection of general signals is effectively enabled.
JP20470187A 1987-08-17 1987-08-17 Master slice type semiconductor integrated circuit Expired - Lifetime JPH0646653B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20470187A JPH0646653B2 (en) 1987-08-17 1987-08-17 Master slice type semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20470187A JPH0646653B2 (en) 1987-08-17 1987-08-17 Master slice type semiconductor integrated circuit

Publications (2)

Publication Number Publication Date
JPS6446951A true JPS6446951A (en) 1989-02-21
JPH0646653B2 JPH0646653B2 (en) 1994-06-15

Family

ID=16494880

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20470187A Expired - Lifetime JPH0646653B2 (en) 1987-08-17 1987-08-17 Master slice type semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPH0646653B2 (en)

Also Published As

Publication number Publication date
JPH0646653B2 (en) 1994-06-15

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