SU615470A2 - Clock signal generator - Google Patents

Description

(54) TACT SENSOR

The invention relates to the field of computer technology and is intended for the distribution of control signals.

According to the main author. St. 456269 a clock sensor is known that contains an AND-bit register, each bit of which consists of two flip-flops, with the single inputs of the first flip-flops of each bit connected / to the zero outputs of the second flip-flops of the same bit, and the single outputs with the input clock device skhemu1 Q-NOT, a first input connected to the zero input of the first flip-flop of the discharge unit and the input of the first trigger adjacent the least significant bit, a second input-output of the first trigger unit of the discharge, and output - with zero WMOs th second trigger neighboring MSB. The disadvantage of this sensor is unsatisfactory performance characteristics.

The aim of the invention is to improve the axigate characteristics of the clock sensor which consists in the possibility of

control the number of channels of distribution of hapulses in the absence of direct / s tact.

This is achieved by tem | that the clock sensor contains an additional trshter and an inverter, and the output of the last bit NAND circuit is connected to a single input of an additional trigger, the zero output of which is connected to the zero input of the first trigger of the last bit and via an inverter: to the second unit outputs of the second triggers of all bits , the third single trigger inputs are connected to the control | tires of the corresponding bits, their fourth single inputs, as well as the zero input of an additional trigger to the clock pulse bus.

The drawing shows a clock sensor circuit for four bits.

It contains a clock pulse bus 1, bit control busses 2-5, logic elements, which in pairs form the second triggers of the first fourth, respectively, of bits 6-13, the first

heras 14-17, cxxeNOJ tt-HE, AND-NOT schemes, o6paraschie additional triggers, inverter 24, inverters 25-28, outputs 29-44 of the clock sensor,

Ify (ieBHe outputs of the second triggers (outputs of elements 7.9, 11, 13) are connected with single inputs of the first trinders of the corresponding bits, with zero inputs of the first rows: 9 first inputs of the first rows of AND-18 -21, Single origin of the flip-flops 14-17 are connected, about the second inputs of circuits 18-21, the outputs of which are connected to the single inputs of the second triggers of the next bits (with the inputs of the elements 8,10,12), the output of the circuit IS-NOT 21 of the last fourth bit yes connected to the single input of the additional trigger (with the input of the circuit IS-NOT 22), vuli in The output of the additional trigger (output of the IS-NO 23 circuit) is connected to the zero input of the first trigger of the fourth bit 17 and through the 24fc inverter with the second single BTOW inputs, which trigger all bits (with the inputs of the elements 7.9, 11, 13), and the third the inputs of which are connected to the inputs of the second triggers (with the inputs of the elements .7, 9, 11, 13), as well as with the zero input of an additional trigger (with the input of the circuit 23).

The device works as follows,.

In the ncode state, the first trigger 17 of the fourth bit will be in

the unit state, the remaining triggers are in the zero state. Let, for example, at control input 3 be a logical unit, at the remaining inputs a logical zero, at the outputs of elements 7, 9, 11, 13, 18, 19, 20, 22, 23, 25, 26, 27, 28 - logical unit, at the outputs of elements 6, 8, 1О, 12,; 2l, 24 - logical zero. With prihoch. The home of the clock pulse at the output of the NANDI circuit 23 appears a signal equal to logical nush, which sets the fourth-bit trigger 17 to the zero state. Since at the control input there is a 3-unit unit, then at the output of flip-flop 9 a signal equal to logical zero appears, which sets the flip-flop 15 of the second bit to one state. The presence of connections from the output of the circuit AND-NOT 23 to the input of the circuit AND-NOT 22 and from the output of trigger 8 to the input of the circuit IS-NOT 19 prevents the output of the circuits AND-NOT 19 and 22 (at the time of the clock pulse)

signals equal LOGIChir Kn v. triggers 15 and 17 and changed their state. Thus, at the trigger output, a signal is generated, the length of which is equal to the duration of the clock pulse and which arrives at the output 35, and at the zero output of the Hera 15 motor, a signal appears that is equal to the duration of the clock pulse and which enters the output bus 42, Upon the completion of the clock pulse, the output of the IS-NE 23 circuit is set to one, and the output of the inverter 24 (logical zero. As a result, the output of the flip-flop 9 is set to one, and the output of the IS-HE circuit 19 appears drove equal to a logical zero, with a duration equal to the duration of the clock pulse; the output of the inverter 27 is a signal whose duration is equal to the period of the clock pulses, With the arrival of the subsequent clock at the output of the trigger 11, the trigger 16 is set to one state, and the trigger 15 is in the zero state. At this output 37, a signal is generated whose duration is equal to the duration of a clock pulse, and a signal is generated at output 43, the duration of which is equal to | clock pulses. The presence of connections from the output of the trigger 11 to the inputs of the trigger 10 and the AND-NOT circuit 20 prevents the appearance of a logical zero at the outputs of these circuits. The signals are distributed over the remaining output buses in a similar way, and with the third clock pulse, the circuit returns to its original state.

Thus, if there is a control signal at the third input, the air conditioner & device has a full cycle of signal distribution for the three-cycle clock pulse following. To increase the number of output channels and to increase the distribution cycle, and the control signal is fed to bus 2, in this case, the signal distribution cycle will be equal to four periods of the clock pulse. If there is a control signal at the fourth input, the nickel of the signal distribution will be equal to two periods of following clock pulses.

Thus, the proposed clock sensor allows organizing the distribution of signals with a variable cycle, and the specific value of the cycle value is set by the control signal