JPS6442183A - Method of packaging semiconductor device - Google Patents
Method of packaging semiconductor deviceInfo
- Publication number
- JPS6442183A JPS6442183A JP19850887A JP19850887A JPS6442183A JP S6442183 A JPS6442183 A JP S6442183A JP 19850887 A JP19850887 A JP 19850887A JP 19850887 A JP19850887 A JP 19850887A JP S6442183 A JPS6442183 A JP S6442183A
- Authority
- JP
- Japan
- Prior art keywords
- board
- chip
- transparent
- parts
- chip mounting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
Abstract
PURPOSE:To facilitate packaging of chips accurately and facilitate batch processing of wirings between electrodes with every chip mounting board as a unit of processing by a method wherein recessed parts for absorbing the difference in chip thickness are provided in the chip mounting board and an evaporation wiring method or a printing wiring method is applied. CONSTITUTION:Ultraviolet and heat curing type resin is applied to the whole main surface of a board 1. After chips 3a and 3b are put in the recessed parts 2 of the board 1, a transparent board is put on the main surface of the board and a pressure is applied to the transparent board. Ultraviolet rays are applied to the resin through the transparent board with the transparent board fixed by pressure and, further, the resin in the parts where the ultraviolet rays can not reach is cured by heat. Then the transparent board is removed and, after an insulating film 9 is formed over the whole surface except electrode parts, electrode wirings 12 are formed by an evaporation method or a printing method. With this constitution, the chip mounting board which has the recessed parts absorbs the difference in chip thickness and the inclination of the chip and the step between the chip and the board produced at the time of die-bonding are corrected to keep the surface of the chip and the surface of the board in the same plane and the electrode wirings for mounting can be formed by batch processing with every chip mounting board as a unit of processing by utilizing an evaporation method or a printing method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62198508A JP2532496B2 (en) | 1987-08-07 | 1987-08-07 | Semiconductor device mounting method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62198508A JP2532496B2 (en) | 1987-08-07 | 1987-08-07 | Semiconductor device mounting method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6442183A true JPS6442183A (en) | 1989-02-14 |
JP2532496B2 JP2532496B2 (en) | 1996-09-11 |
Family
ID=16392302
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62198508A Expired - Fee Related JP2532496B2 (en) | 1987-08-07 | 1987-08-07 | Semiconductor device mounting method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2532496B2 (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004184797A (en) * | 2002-12-05 | 2004-07-02 | Seiko Epson Corp | Electronic device, its manufacturing method and electronic equipment |
JP2013093453A (en) * | 2011-10-26 | 2013-05-16 | Nippon Dempa Kogyo Co Ltd | Electronic module and manufacturing method therefor |
JP2017092092A (en) * | 2015-11-04 | 2017-05-25 | 豊田合成株式会社 | Method of manufacturing light-emitting device |
CN107833903A (en) * | 2016-09-15 | 2018-03-23 | 伊乐视有限公司 | Active display with light management system |
CN111640708A (en) * | 2020-06-22 | 2020-09-08 | 武汉华星光电半导体显示技术有限公司 | Display module, manufacturing method thereof and electronic equipment |
-
1987
- 1987-08-07 JP JP62198508A patent/JP2532496B2/en not_active Expired - Fee Related
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004184797A (en) * | 2002-12-05 | 2004-07-02 | Seiko Epson Corp | Electronic device, its manufacturing method and electronic equipment |
JP2013093453A (en) * | 2011-10-26 | 2013-05-16 | Nippon Dempa Kogyo Co Ltd | Electronic module and manufacturing method therefor |
JP2017092092A (en) * | 2015-11-04 | 2017-05-25 | 豊田合成株式会社 | Method of manufacturing light-emitting device |
CN107833903A (en) * | 2016-09-15 | 2018-03-23 | 伊乐视有限公司 | Active display with light management system |
CN111640708A (en) * | 2020-06-22 | 2020-09-08 | 武汉华星光电半导体显示技术有限公司 | Display module, manufacturing method thereof and electronic equipment |
CN111640708B (en) * | 2020-06-22 | 2022-08-05 | 武汉华星光电半导体显示技术有限公司 | Display module, manufacturing method thereof and electronic equipment |
Also Published As
Publication number | Publication date |
---|---|
JP2532496B2 (en) | 1996-09-11 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
LAPS | Cancellation because of no payment of annual fees |