JPS6419752A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS6419752A
JPS6419752A JP62176340A JP17634087A JPS6419752A JP S6419752 A JPS6419752 A JP S6419752A JP 62176340 A JP62176340 A JP 62176340A JP 17634087 A JP17634087 A JP 17634087A JP S6419752 A JPS6419752 A JP S6419752A
Authority
JP
Japan
Prior art keywords
bumps
lsi chip
leads
short
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62176340A
Other languages
Japanese (ja)
Other versions
JP2623578B2 (en
Inventor
Yuji Iwata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62176340A priority Critical patent/JP2623578B2/en
Publication of JPS6419752A publication Critical patent/JPS6419752A/en
Application granted granted Critical
Publication of JP2623578B2 publication Critical patent/JP2623578B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto

Abstract

PURPOSE:To prevent the damage to a protective film on the surface of LSI chip and a surface layer as well as the short-circuit between leads and semiconductor chip ends from occurring by a method wherein auxiliary bumps such as short-circuit preventive auxiliary bumps, etc., are arranged outside connecting bumps on a semiconductor chip. CONSTITUTION:Connecting bumps 2 for power supply and input output signals are arranged zigzag on the four side peripheral parts on the surface of an LSI chip 1 while auxiliary bumps 3 and short-circuit preventive auxiliary bumps 4 are provided outside those connecting bumps 2. Then, the damage to a protective film 5 on the surface of LSI chip from leads 6 due to the pressure of bonding tool during bonding process as well as the cracking of the surface layer of LSI chip can be prevented from occurring. Furthermore, the short-circuit between leads and the ends of LSI chip due to the deformation of leads 6 during bonding process and later operational processes can be prevented from occurring.
JP62176340A 1987-07-14 1987-07-14 Semiconductor integrated circuit device Expired - Lifetime JP2623578B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62176340A JP2623578B2 (en) 1987-07-14 1987-07-14 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62176340A JP2623578B2 (en) 1987-07-14 1987-07-14 Semiconductor integrated circuit device

Publications (2)

Publication Number Publication Date
JPS6419752A true JPS6419752A (en) 1989-01-23
JP2623578B2 JP2623578B2 (en) 1997-06-25

Family

ID=16011871

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62176340A Expired - Lifetime JP2623578B2 (en) 1987-07-14 1987-07-14 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JP2623578B2 (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0459493A2 (en) * 1990-06-01 1991-12-04 Kabushiki Kaisha Toshiba A semiconductor device using a lead frame and its manufacturing method
JPH04372144A (en) * 1991-06-21 1992-12-25 Nec Corp Tab type semiconductor device
EP0645806A1 (en) * 1993-04-08 1995-03-29 Seiko Epson Corporation Semiconductor device
US5556810A (en) * 1990-06-01 1996-09-17 Kabushiki Kaisha Toshiba Method for manufacturing a semiconductor device wherein a semiconductor chip is connected to a lead frame by metal plating
EP0755075A2 (en) * 1995-06-29 1997-01-22 Sharp Kabushiki Kaisha A tape carrier package
JPH09129809A (en) * 1995-10-31 1997-05-16 Nec Corp Semiconductor device and its manufacture
US6049121A (en) * 1996-04-24 2000-04-11 Sharp Kabushiki Kaisha Tape carrier package and liquid crystal display device including such tape carrier package
JP2005117036A (en) * 2003-10-04 2005-04-28 Samsung Electronics Co Ltd Tape circuit board and semiconductor chip package utilizing same

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3516608B2 (en) * 1999-04-27 2004-04-05 沖電気工業株式会社 Semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53123074A (en) * 1977-04-01 1978-10-27 Nec Corp Semiconductor device
JPS62125649A (en) * 1985-11-26 1987-06-06 Nec Corp Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53123074A (en) * 1977-04-01 1978-10-27 Nec Corp Semiconductor device
JPS62125649A (en) * 1985-11-26 1987-06-06 Nec Corp Semiconductor device

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5556810A (en) * 1990-06-01 1996-09-17 Kabushiki Kaisha Toshiba Method for manufacturing a semiconductor device wherein a semiconductor chip is connected to a lead frame by metal plating
EP0459493A3 (en) * 1990-06-01 1994-02-23 Toshiba Kk
EP0459493A2 (en) * 1990-06-01 1991-12-04 Kabushiki Kaisha Toshiba A semiconductor device using a lead frame and its manufacturing method
US5654584A (en) * 1990-06-01 1997-08-05 Kabushiki Kaisha Toshiba Semiconductor device having tape automated bonding leads
JPH04372144A (en) * 1991-06-21 1992-12-25 Nec Corp Tab type semiconductor device
EP0645806A1 (en) * 1993-04-08 1995-03-29 Seiko Epson Corporation Semiconductor device
US5563445A (en) * 1993-04-08 1996-10-08 Seiko Epson Corporation Semiconductor device
EP0645806A4 (en) * 1993-04-08 1995-10-11 Seiko Epson Corp Semiconductor device.
EP0755075A2 (en) * 1995-06-29 1997-01-22 Sharp Kabushiki Kaisha A tape carrier package
EP0755075A3 (en) * 1995-06-29 1998-12-09 Sharp Kabushiki Kaisha A tape carrier package
KR100225924B1 (en) * 1995-06-29 1999-10-15 마찌다 가쯔히꼬 Tape carrier package
JPH09129809A (en) * 1995-10-31 1997-05-16 Nec Corp Semiconductor device and its manufacture
US6049121A (en) * 1996-04-24 2000-04-11 Sharp Kabushiki Kaisha Tape carrier package and liquid crystal display device including such tape carrier package
KR100256911B1 (en) * 1996-04-24 2000-05-15 마찌다 가쯔히꼬 Tape carrier package and liquid crystal display device including such tape carrier package
JP2005117036A (en) * 2003-10-04 2005-04-28 Samsung Electronics Co Ltd Tape circuit board and semiconductor chip package utilizing same

Also Published As

Publication number Publication date
JP2623578B2 (en) 1997-06-25

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