JPS6442160A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6442160A
JPS6442160A JP18569388A JP18569388A JPS6442160A JP S6442160 A JPS6442160 A JP S6442160A JP 18569388 A JP18569388 A JP 18569388A JP 18569388 A JP18569388 A JP 18569388A JP S6442160 A JPS6442160 A JP S6442160A
Authority
JP
Japan
Prior art keywords
metal
slice
laminate
fixed
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18569388A
Other languages
Japanese (ja)
Inventor
Chini Karuro
Shisutei Ruigi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SGS THOMSON MICROELECTRONICS
STMicroelectronics SRL
Original Assignee
SGS THOMSON MICROELECTRONICS
SGS Thomson Microelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS THOMSON MICROELECTRONICS, SGS Thomson Microelectronics SRL filed Critical SGS THOMSON MICROELECTRONICS
Publication of JPS6442160A publication Critical patent/JPS6442160A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements

Abstract

PURPOSE: To enable mass production by providing a metal laminate formed on a metal slice, separated by and from an electric insulation layer integrated with at least one of metal electrodes and chip semiconductor element electrically contacted and fixed to this laminate. CONSTITUTION: Inside a synthetic resin body 4 are provided a metal laminate 12, provided on a metal slice 2 separated by and from an electric insulation layer integrated with at least one of metal electrodes 10 and a chip semiconductor element 14, electrically contacted and fixed to this laminate 12. A first chip semiconductor element 6, including an integrated circuit, is fixed to the slice 2 by, e.g. brazing the base electrode and slice surface. Thus it is possible to manufacture a semiconductor device in a 'multi-watt' type standard case, using the same machine and manufacturing process as is usually used for the semiconductor device manufacturing and hence, enables executing a very economical mass production.
JP18569388A 1987-07-28 1988-07-27 Semiconductor device Pending JPS6442160A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT214787 1987-07-28

Publications (1)

Publication Number Publication Date
JPS6442160A true JPS6442160A (en) 1989-02-14

Family

ID=11102751

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18569388A Pending JPS6442160A (en) 1987-07-28 1988-07-27 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6442160A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50155967A (en) * 1974-06-07 1975-12-16
JPS5999753A (en) * 1982-11-10 1984-06-08 ブラウン・ボバリ・ウント・シ−・アクチエンゲゼルシヤフト Power transistor module

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50155967A (en) * 1974-06-07 1975-12-16
JPS5999753A (en) * 1982-11-10 1984-06-08 ブラウン・ボバリ・ウント・シ−・アクチエンゲゼルシヤフト Power transistor module

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