JPS6441312A - Semiconductor delay circuit device - Google Patents

Semiconductor delay circuit device

Info

Publication number
JPS6441312A
JPS6441312A JP62196904A JP19690487A JPS6441312A JP S6441312 A JPS6441312 A JP S6441312A JP 62196904 A JP62196904 A JP 62196904A JP 19690487 A JP19690487 A JP 19690487A JP S6441312 A JPS6441312 A JP S6441312A
Authority
JP
Japan
Prior art keywords
delay
component
inverter
circuit
constitution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62196904A
Other languages
Japanese (ja)
Inventor
Kazuto Tanahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP62196904A priority Critical patent/JPS6441312A/en
Publication of JPS6441312A publication Critical patent/JPS6441312A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To obtain a large delay with small circuit constitution by controlling the delay of a logic gate by an output current of a MOST being a component of a current mirror circuit together with a MOST being a component of a constant current source circuit. CONSTITUTION:A 1st P-channel MOS transistor (P-MOST)QP1 being a component of the constant current source circuit 1 and a 4th P-MOSTQP4 being a component of a current mirror circuit are interposed between an inverter 2 and a power voltage VDD. Thus, the delay of the inverter 2 is controlled by an output current I3 of the 4th P-MOSTQP4. In adjusting the output current IP4, the delay of the inverter 2 is set to an optional value. Thus, a large delay is obtained regardless of small circuit constitution.
JP62196904A 1987-08-06 1987-08-06 Semiconductor delay circuit device Pending JPS6441312A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62196904A JPS6441312A (en) 1987-08-06 1987-08-06 Semiconductor delay circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62196904A JPS6441312A (en) 1987-08-06 1987-08-06 Semiconductor delay circuit device

Publications (1)

Publication Number Publication Date
JPS6441312A true JPS6441312A (en) 1989-02-13

Family

ID=16365578

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62196904A Pending JPS6441312A (en) 1987-08-06 1987-08-06 Semiconductor delay circuit device

Country Status (1)

Country Link
JP (1) JPS6441312A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1992016051A1 (en) * 1991-03-05 1992-09-17 Vlsi Technology, Inc. Cmos delay circuit with controllable delay
US6157865A (en) * 1997-06-13 2000-12-05 Mattel, Inc. User-created curios made from heat-shrinkable material
JP2006352741A (en) * 2005-06-20 2006-12-28 Nec Electronics Corp Dead time control circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1992016051A1 (en) * 1991-03-05 1992-09-17 Vlsi Technology, Inc. Cmos delay circuit with controllable delay
US6157865A (en) * 1997-06-13 2000-12-05 Mattel, Inc. User-created curios made from heat-shrinkable material
JP2006352741A (en) * 2005-06-20 2006-12-28 Nec Electronics Corp Dead time control circuit

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