JPS6441142U - - Google Patents

Info

Publication number
JPS6441142U
JPS6441142U JP13570187U JP13570187U JPS6441142U JP S6441142 U JPS6441142 U JP S6441142U JP 13570187 U JP13570187 U JP 13570187U JP 13570187 U JP13570187 U JP 13570187U JP S6441142 U JPS6441142 U JP S6441142U
Authority
JP
Japan
Prior art keywords
island
lead frame
lead
semiconductor chip
circuit device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13570187U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP13570187U priority Critical patent/JPS6441142U/ja
Publication of JPS6441142U publication Critical patent/JPS6441142U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例を示すプラスチツク
・モールド・フラツトタイプ半導体集積回路装置
の斜視図、第2図は本考案の他の実施例を示すプ
ラスチツク・モールド・フラツトタイプ半導体集
積回路装置の斜視図である。 1……半導体チツプのプラスチツク・モールド
体、2……フラツト・リード端子、3……プリツ
ジ部、4……リード・フレームの外枠部、4a〜
4d……リード・フレームの外枠部の曲折載片。
FIG. 1 is a perspective view of a plastic mold flat type semiconductor integrated circuit device showing one embodiment of the present invention, and FIG. 2 is a perspective view of a plastic mold flat type semiconductor integrated circuit device showing another embodiment of the invention. It is. DESCRIPTION OF SYMBOLS 1...Plastic molded body of semiconductor chip, 2...Flat lead terminal, 3...Printer part, 4...Outer frame part of lead frame, 4a~
4d...A bent piece for the outer frame of the lead frame.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] リードレームのアイランド上に載置される半導
体チツプのプラスチツク・モールド体と、前記半
導体チツプとボンデイング接続されるリードフレ
ームのフラツト・リード端子配列と、前記リード
端子以外をブリツジ部として前記アイランドの周
辺にアイランドと一体化構造で残されるリードフ
レームの外枠部から成る放熱板とを含むことを特
徴とする半導体集積回路装置。
A plastic molded body of a semiconductor chip placed on an island of a lead frame, a flat lead terminal arrangement of a lead frame bonded to the semiconductor chip, and a bridge portion other than the lead terminals arranged around the island. 1. A semiconductor integrated circuit device comprising: an island; and a heat dissipation plate consisting of an outer frame portion of a lead frame left in an integrated structure.
JP13570187U 1987-09-04 1987-09-04 Pending JPS6441142U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13570187U JPS6441142U (en) 1987-09-04 1987-09-04

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13570187U JPS6441142U (en) 1987-09-04 1987-09-04

Publications (1)

Publication Number Publication Date
JPS6441142U true JPS6441142U (en) 1989-03-13

Family

ID=31395564

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13570187U Pending JPS6441142U (en) 1987-09-04 1987-09-04

Country Status (1)

Country Link
JP (1) JPS6441142U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007150044A (en) * 2005-11-29 2007-06-14 Denso Corp Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007150044A (en) * 2005-11-29 2007-06-14 Denso Corp Semiconductor device

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