JPS6439753A - Manufacture of integrated circuit device - Google Patents
Manufacture of integrated circuit deviceInfo
- Publication number
- JPS6439753A JPS6439753A JP62196753A JP19675387A JPS6439753A JP S6439753 A JPS6439753 A JP S6439753A JP 62196753 A JP62196753 A JP 62196753A JP 19675387 A JP19675387 A JP 19675387A JP S6439753 A JPS6439753 A JP S6439753A
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- metal wire
- fine metal
- integrated circuit
- sealing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
PURPOSE:To prevent a fine metal wire and a lead frame from contacting each other due to deformation and the like and short-circuiting between terminals during transportation and each process of assembly, by forming and then sealing an insulating coating on the surface of the fine metal wire and the lead frame after the fine metal wire is connected. CONSTITUTION:An integrated circuit 2 is connected by a fine metal wire 3 after mounted on a lead frame 5, and than heated in an oxygen atmosphere. As a result, an insulating oxide coating 4 is formed on the surface of the fine metal wire and the lead frame. Thereafter, sealing is performed by a sealing resin 1 and a portion D to be used in soldering an oxide coating of the lead frame is removed by etching.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62196753A JPS6439753A (en) | 1987-08-05 | 1987-08-05 | Manufacture of integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62196753A JPS6439753A (en) | 1987-08-05 | 1987-08-05 | Manufacture of integrated circuit device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6439753A true JPS6439753A (en) | 1989-02-10 |
Family
ID=16363040
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62196753A Pending JPS6439753A (en) | 1987-08-05 | 1987-08-05 | Manufacture of integrated circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6439753A (en) |
-
1987
- 1987-08-05 JP JP62196753A patent/JPS6439753A/en active Pending
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