JPS6439120A - Clock generator - Google Patents

Abstract

PURPOSE:To finely change the period without using a high-speed clock by using the delay time of a delay line to change the period less than an input clock. CONSTITUTION:The output has delay times 0, , 2 and 3 against the clock signal phi supplied to a delay line 1 and the period of the signal phi is set at 4 . A selector 2 selects the output DO2 of the line 1 as long as a selection signal S1 is equal to '1'. Thus the output phiSYS is approximate to the output DO2. The output of a NAND gate 5 is changed to '1' at a time point T1 and the output phiSYS is supplied to a ring counter 3 via an AND gate 6. The output of the gate 6 changes to '1' at a time point T2 together with the output S2 of the counter 3 changed to '0', the signal S1 changed to '1' and the output phiSYS changed to '0' respectively. Subsequently, same changes are carried out and the phase of the output phiSYS advances by 3 compared with a case where no clock signal is outputted to the counter 3.