JPS5611529A - Microprogram control unit - Google Patents

Microprogram control unit

Info

Publication number
JPS5611529A
JPS5611529A JP8595979A JP8595979A JPS5611529A JP S5611529 A JPS5611529 A JP S5611529A JP 8595979 A JP8595979 A JP 8595979A JP 8595979 A JP8595979 A JP 8595979A JP S5611529 A JPS5611529 A JP S5611529A
Authority
JP
Japan
Prior art keywords
low speed
control unit
clock
gate
microprogram control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8595979A
Other languages
Japanese (ja)
Inventor
Tsuneo Horie
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP8595979A priority Critical patent/JPS5611529A/en
Publication of JPS5611529A publication Critical patent/JPS5611529A/en
Pending legal-status Critical Current

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  • Information Transfer Systems (AREA)
  • Multi Processors (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE: To enable the low speed operation in synchronizing with the low speed unit, by generating the clock for one cycle's share every incoming of start signal, in operating the control unit through connecting to low speed microprogram control unit.
CONSTITUTION: FF12...15 constitute the ring counter and operate as the clock circuit. Further, when the mode switching signal is switched to "0" level, the AND circuits 16, 19 are closed, the output of FF15 is fed to FF12 via the AND gate 19, and the basic clock T is fed to FF15 via the AND gate 17. Further, the gate 19 is open only when the start signal LSTART of "1" level is given externally. Accordingly, in operating in connection with the microprogram control unit of low speed, the clock for one cycle's share in produced every incoming of start signal, allowing to perform low speed operation in synchronizing with the low speed unit.
COPYRIGHT: (C)1981,JPO&Japio
JP8595979A 1979-07-09 1979-07-09 Microprogram control unit Pending JPS5611529A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8595979A JPS5611529A (en) 1979-07-09 1979-07-09 Microprogram control unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8595979A JPS5611529A (en) 1979-07-09 1979-07-09 Microprogram control unit

Publications (1)

Publication Number Publication Date
JPS5611529A true JPS5611529A (en) 1981-02-04

Family

ID=13873275

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8595979A Pending JPS5611529A (en) 1979-07-09 1979-07-09 Microprogram control unit

Country Status (1)

Country Link
JP (1) JPS5611529A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60649U (en) * 1983-06-17 1985-01-07 日本電気株式会社 Multi-CPU system synchronization device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60649U (en) * 1983-06-17 1985-01-07 日本電気株式会社 Multi-CPU system synchronization device

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