JPS57204628A - Clock generating circuit - Google Patents

Clock generating circuit

Info

Publication number
JPS57204628A
JPS57204628A JP8917981A JP8917981A JPS57204628A JP S57204628 A JPS57204628 A JP S57204628A JP 8917981 A JP8917981 A JP 8917981A JP 8917981 A JP8917981 A JP 8917981A JP S57204628 A JPS57204628 A JP S57204628A
Authority
JP
Japan
Prior art keywords
output
signal
circuit
high level
low level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8917981A
Other languages
Japanese (ja)
Other versions
JPH0237728B2 (en
Inventor
Hisakatsu Kubota
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP8917981A priority Critical patent/JPS57204628A/en
Publication of JPS57204628A publication Critical patent/JPS57204628A/en
Publication of JPH0237728B2 publication Critical patent/JPH0237728B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Electronic Switches (AREA)

Abstract

PURPOSE:To prevent a reduction of output pulse duration, by discontinuing a continuous clock signal by means of an NOR circuit and by the selecting signal, at the same time supplying the single-shot clock generation indicating signal to the NOR circuit and producing the single-shot clock signals with the same phase and synchronously with the continuous clock signal. CONSTITUTION:When a single-shot clock generation indicating signal 2 and a selecting signal 3 are at a low level, respectively, the output of an NOR circuit N4 is set at a low level. The output of an NOR circuit N5 is set at a low level since the output Q' of a flip-flop 4 is set at a high level. As a result, the output of an NOR circuit N6 is set at a low level to obtain a continuous clock signal from an output 12. When the signal 3 is set at a high level, the output of the N5 is set at a low level. Then the output of the N6 is set at a high level to discontinue the output 12. When the signal 2 is set at a high level, the output of the N5 is set at a high level for a clock period. Thus a single-shot pulse is obtained at the output 12.
JP8917981A 1981-06-10 1981-06-10 Clock generating circuit Granted JPS57204628A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8917981A JPS57204628A (en) 1981-06-10 1981-06-10 Clock generating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8917981A JPS57204628A (en) 1981-06-10 1981-06-10 Clock generating circuit

Publications (2)

Publication Number Publication Date
JPS57204628A true JPS57204628A (en) 1982-12-15
JPH0237728B2 JPH0237728B2 (en) 1990-08-27

Family

ID=13963527

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8917981A Granted JPS57204628A (en) 1981-06-10 1981-06-10 Clock generating circuit

Country Status (1)

Country Link
JP (1) JPS57204628A (en)

Also Published As

Publication number Publication date
JPH0237728B2 (en) 1990-08-27

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