JPH0237728B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a clock generation circuit in a computer, and particularly to a clock generation circuit in a computer.
This relates to a circuit that generates a one-shot clock necessary to check the status every time.

FIG. 1 shows a conventional clock generation circuit, and FIG. 1a is a configuration diagram, in which 1 is a continuous clock signal terminal, 2 is a single-shot clock generation instruction signal terminal, 3 is a selection signal, and 4 is a block diagram of a conventional clock generation circuit.
is a single clock generation circuit, 5 is a switching circuit, 6, 7
is a negative circuit, 8 is a NOR circuit, 9 and 10 are AND circuits, 11 is an OR circuit, 12 is an output terminal, FF1~
FF3 is an edge trigger type D flip-flop.
11 to 15 indicate signal lines, and FIGS. 1b and 1c are timing charts for each signal line and terminal. Note that the continuous clock signal is connected to the single-shot clock generation circuit 4 and the switching circuit 5, and is switched between the continuous clock signal and the output of the single-shot clock generation circuit 4 according to the output of the single-shot clock generation circuit 4 and the selection signal, and is sent to the output terminal 12. Output to.

Next, the operation will be explained. Selection signal terminal 3 is “0”
At this time, the continuous clock signal supplied to the clock signal terminal 1 passes through the AND circuit 10 and the OR circuit 11 to the output terminal as it is because the selection signal terminal is "0" and the NOT circuit 7 is "1" as shown in FIG. 1b. 12. However, if the selection signal switches from "0" to "1" (or from "1" to "0") midway through, the normal pulse width may not be output depending on the switching timing, and a very narrow pulse may be output. It may be output. Such narrow width pulses are unfavorable for logic circuit operation and can cause malfunctions.For example, when multiple latch circuits receive narrow width clocks at the same time, some of them may operate while others may fail due to variations in their sensitivities. This can lead to problems such as the circuit state not being determined because it does not work.

Therefore, when debugging involves stopping the continuous clock and inspecting the internal state of the computer, the accurate internal state cannot be seen, which is inconvenient for debugging.

Next, the operation of outputting a single clock by setting the single clock generation instruction signal to "1" when the selection signal is "1" will be explained using FIG. 1c.

A continuous clock is shown in FIG. It is assumed that flip-flops FF1 to FF3 (hereinafter referred to as FF) change at the rising edge as shown by the arrow on the signal line l1, and _T1 to _T9 are timings, respectively. When the single clock generation instruction signal terminal 2 is "0", the signal line l2 is "0", the signal line _l3 is "1", the NOR circuit 8 outputs "0", and the circuit terminal 12 is "0". Next, when the single clock generation instruction signal terminal 2 becomes "1" at a timing between T ₃ and T ₄ , for example, FF1 is determined by the D input, so the timing T ₄ of the signal line l1
The status changes to “1” at the rising edge of . At the next timing _T5 , the signal line l2 becomes "1",
The state of FF2 becomes "1". The signals l3 and l4 are "0", and when the signal line l1 becomes "0", the NOR circuit 8 changes to "1". At timing _T6 , the signal line l1 becomes "1", the FF3 becomes "0", and the signal line l4 becomes "1". Therefore, output for one pulse is present at the output terminal 12. Note that when the single clock generation instruction signal terminal 2 returns from "1" to "0", each FF
changes in the opposite way to the above, but the inputs to the NOR circuit do not all become "0", and the output terminal 12 remains "0" (as shown in Figure 1c).

Therefore, one single clock is output only when the selection signal terminal 3 changes from "0" to "1".

According to this conventional circuit, the route taken by the continuous clock and the route taken by the single clock are different, so the timings of the continuous clock and the single clock do not match.

If the timings do not match, the operation timings of the part operating with a continuous clock and the part supplied with a single clock will be different, and debugging etc. will not be successful.

One of the objects of the present invention is to eliminate the conventional disadvantage of shortening the pulse width, and another object of the present invention is to match the paths of the continuous clock and the single-shot clock. The purpose of this is to provide a selection signal synchronization means for synchronizing the selection signal with the continuous clock, and a single-shot clock generation instruction signal in a clock generation circuit that can arbitrarily select and generate continuous clock pulses and single-shot clock pulses using a selection signal. a single clock signal synchronization means for synchronizing with the continuous clock; a NOR circuit for synchronizing the output of the selection signal synchronization means and the output of the single clock signal synchronization means with the continuous clock; This is achieved by a clock generation circuit characterized in that one input terminal is provided with a set-reset type flip-flop to which the continuous clock pulse is inputted to the other input terminal.

Hereinafter, the present invention will be explained in detail using FIG. 2.

FIG. 2 shows an embodiment of the invention. FIG. 2a is a block diagram of the present invention, in which 1 is a continuous clock signal terminal, 2 is a single-shot clock generation instruction signal terminal, 3 is a selection signal terminal, 12 is an output terminal, FF1 to FF5 are edge trigger type D flip-flops, L1 to L10 is a signal line, N1 to N7 are NOR circuits, 13 is flip-flop FF1, FF2, FF3, NOR circuit N4
Single clock signal synchronization means consisting of 14 is FF
4, selection signal synchronization means 15 consisting of FF5, NOR circuits N5, N6, and N7, the selection signal synchronization means 14 and the single clock signal synchronization means 13;
Figure 2b is a timing chart for each signal line and terminal. Note that the same symbols as in the previous figure indicate the same items as in the previous figure. Also, NOR circuit N6, N
7 constitutes a set/reset type flip-flop.

In the present invention, the continuous clock signal input from the continuous clock terminal 1 is connected to the NOR circuit N7 by the selection signal.
In this state, a single clock generation instruction signal is input from the single clock generation instruction signal terminal 2, and the NOR circuit N7 outputs a single clock in synchronization with the continuous clock signal in the same phase.When the selection signal is released, the continuous clock is started again. It is designed to be output.

Hereinafter, the operation of the present invention will be explained in order.

First, a state in which "0" is supplied to the selection signal terminal 3 will be explained. A continuous clock signal is input at terminal 1 and supplied to each flip-flop. Both the single clock generation instruction signal and the selection signal are in the "0" state.

Therefore, the single clock generation instruction signal is “0”.
Therefore, FF1 becomes "0", FF2 becomes "0", FF3 becomes "1", and NOR circuit N4 sends "0" to the signal line L.
Output to 5. Also, since the selection signal is “0”, it is FF
Since the signal line L5 which outputs "1" to the signal line L6 is "0" and the signal line L6 is "1", the NOR circuit N5 outputs "0" and FF5 becomes "0". Since FF5 is "0", the output signal line L8 becomes "1", and the NOR circuit N6 outputs "0" regardless of the logic state of the output terminal 12. Therefore, since the signal line L9 is "0", the output of the NOR circuit N7 also becomes "0" and "1" in response to the continuous clock signals "0" and "1" passing through the NOR circuits N2 and N3. That is, a continuous clock is output to the output terminal 12.

Next, since the selection signal is “0”, it is “1”, that is,
The operation when stopping the continuous clock will be explained.

For example, suppose that the selection signal "0" changes from "0" to " ₁ " at timing t1 as shown in FIG. 2a. Since FF4 becomes "1" at timing _t2 , signal line L6 becomes "0" (ie, synchronized). In the NOR circuit N5, on the signal line L5 side, the signal state of the single clock generation instruction signal terminal 2 remains unchanged and is therefore "0", and L7 changes to "1". At the next timing _t4 , FF5 becomes "1" because the signal line L7 is "1", and the signal line L8 becomes "0".

The output of the output terminal 12 is "0", and since the signal line L8 of the NOR circuit 6 is "0", the signal line L9 is "1".
Change to At the same time, the NOR circuit N7 becomes "0" regardless of the continuous clock signal, and the output terminal 12
"0" is outputted from the output terminal 12, and the output of the continuous clock to the output terminal 12 is stopped.

Next, when the continuous clock is stopped, for example, if the single clock generation instruction signal changes from "0" to "1" at timing _t5 shown in FIG. _2b , then FF1 becomes "1" at timing t6 (i.e., ,
synchronized). Since the signal line L2 becomes "1" at timing _t6 , FF2 becomes "1" at timing _t8 , and the signal line L3 becomes "0", which is applied to the NOR circuit N4 and FF3. FF3 is timing
At _t10 , it becomes "0" and the signal line L4 changes to "1". Signal lines L3 _and L4 between timing t8 and _t10
becomes "1", and only during that time the NOR circuit N4 outputs "0". As mentioned above, the selection signal is “1”
Therefore, the signal line L6 is "0" and the NOR circuit N
5 outputs " ₁ " between timing t8 and _t10 . Next, from timing _t8 to _t10 , the signal line L
7 is “0” and timing t ₁₀ FF5 is “0”
Therefore, the signal line L8 becomes "1" and the NOR circuit N6 becomes "0" regardless of the circuit state of the output terminal 12. Signal line L9 from timing t ₁₀ to t ₁₂
Since the clock signal is "0" between NOR circuits N2 and N3, NOR circuit N7 outputs "1" to output terminal 12 in response to the continuous clock signal delayed by NOR circuits N2 and N3.

Next, when the output terminal ₁₂ becomes "0" after passing through the three stages of NOR circuits N2, N3, and N7 from t12, L9 becomes "1" because L8 is "0", and then L1
Even if 0 changes from “0” to “1”, the output terminal 12
does not change, so only one single clock is generated.

Next, the operation of outputting a continuous clock will be explained.
For example, when the selection signal is returned from "1" to "0" at timing _t17 , FF4 becomes "0" at timing _t18 , signal line L6 becomes "1", and NOR circuit N5 changes to signal line L.
6 is "1" and L5 is "0", the signal line L7 becomes "0". At timing _t20 , FF5 becomes "0" and outputs "1" to signal line L8. Output terminal 1
2 is "0", the NOR circuit N6 outputs "0" to the signal line L9, so after timing _t21 , the output state of the NOR circuit N3 appears at the output terminal 12, and a continuous clock is output again. will be done.

Note that the NOR circuits N2 and N3 are for delaying the clock signal of the signal line L1 and supplying the delayed clock signal to the NOR circuit N7. so that a single clock of the same phase appears at the output terminal 12.
In particular, it is intended to compensate for circuit operation with a high-speed clock of several tens of nanoseconds. In manufacturing, FF is
Min nanoseconds (hereinafter abbreviated as n) ~ Max8n gates are
Each has a delay of Min1.5n to Max3n, so the delay of L9 with respect to NOR circuit N7 is Min6.5 to Max11n with respect to signal line L1, and the delay of the output of NOR circuits N2 and N3 is with respect to L1. On the other hand, from Min3n~Max6n,
Therefore, they will be adequately compensated.

Even if the signal line L9 has a delay of Max11n, the pulse width of the output of the NOR circuit N3 is not interfered with by the signal line L9, and is output as a synchronized shaped pulse width. Therefore, according to the present invention, since the selection signal and the single clock generation instruction signal are synchronized and used, an undesired pulse width does not occur when successive clocks are stopped and started. Furthermore, since the paths of the single-shot clock and the continuous clock are the same, the same phase as the single-shot clock and the continuous clock is generated, so that a good test can be performed even in a system where a continuous clock generator and a single-shot clock generator coexist.

[Brief explanation of drawings]

Figure 1a is a configuration diagram of a conventional clock generation circuit, Figures 1b and 1c are timing charts for each conventional signal line and terminal, Figure 2a is a configuration diagram of the present invention, and Figure 2b is a diagram for each signal line and terminal. In the timing chart, 1...continuous clock terminal, 2...
Single clock generation instruction signal terminal, 3...Selection signal terminal, 12...Output terminal, FF1 to FF5...D type flip-flop, N1 to N7...NOR circuit, L
1 to L9...signal line, l1 to l5...signal line,
6, 7...Negation circuit, 8...Nor circuit, 9,10
...AND circuit, 11...OR circuit.

Claims (1)

[Claims] 1. In a clock generation circuit that can arbitrarily select and generate continuous clock pulses and single clock pulses using a selection signal, selection signal synchronization means synchronizes the selection signal with the continuous clock, and a single clock generation instruction signal is synchronized with the continuous clock. a single-shot clock signal synchronization means for synchronizing; a NOR circuit for synchronizing the output of the selection signal synchronization means and the output of the single-shot clock signal synchronization means with the continuous clock; and one input of the NOR circuit output. A clock generation circuit characterized in that a set-reset type flip-flop is provided at one end of the circuit, and the continuous clock pulse is inputted to another input end.