JPS6438828A - Lsi circuit with multiswitching mode - Google Patents

Lsi circuit with multiswitching mode

Info

Publication number
JPS6438828A
JPS6438828A JP62196001A JP19600187A JPS6438828A JP S6438828 A JPS6438828 A JP S6438828A JP 62196001 A JP62196001 A JP 62196001A JP 19600187 A JP19600187 A JP 19600187A JP S6438828 A JPS6438828 A JP S6438828A
Authority
JP
Japan
Prior art keywords
circuits
polarities
outputted
those
terminals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62196001A
Other languages
Japanese (ja)
Inventor
Kazunari Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Facom Corp
Original Assignee
Fuji Facom Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Facom Corp filed Critical Fuji Facom Corp
Priority to JP62196001A priority Critical patent/JPS6438828A/en
Publication of JPS6438828A publication Critical patent/JPS6438828A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To reduce the number of gates used in an LSI by sharing gates in plural combinations out of combinations of switching states of one or plural block circuits. CONSTITUTION:When polarities of selector circuits S12-S1n are set to the A side and those of circuits S21-S2n are set to the A side, input signals of external input terminals i11-i1n are outputted to external output terminal O11-O1n through block circuits D11-D1n. When polarities of circuits S12-S1n are set to the B side and those of circuits S21-S2n are set to the A side, the input from the terminal i11 passes the blocks D11 and is not only inputted to the block D12 but also outputted to the terminal O11. When polarities of circuits S12-S1n are set to the A side and those of circuits S21-S2n are set to the B side, input signals of terminals i11-i1n do not pass circuits D but pass by-pass lines and are outputted to terminals O11-O1n. Since circuits S are arranged in this manner, they are shared among three kinds of function and the number of required gates is reduced.
JP62196001A 1987-08-05 1987-08-05 Lsi circuit with multiswitching mode Pending JPS6438828A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62196001A JPS6438828A (en) 1987-08-05 1987-08-05 Lsi circuit with multiswitching mode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62196001A JPS6438828A (en) 1987-08-05 1987-08-05 Lsi circuit with multiswitching mode

Publications (1)

Publication Number Publication Date
JPS6438828A true JPS6438828A (en) 1989-02-09

Family

ID=16350569

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62196001A Pending JPS6438828A (en) 1987-08-05 1987-08-05 Lsi circuit with multiswitching mode

Country Status (1)

Country Link
JP (1) JPS6438828A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57197649A (en) * 1976-05-03 1982-12-03 Ibm Arithmetic logic device
JPS58146949A (en) * 1982-02-26 1983-09-01 Nec Corp General logical circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57197649A (en) * 1976-05-03 1982-12-03 Ibm Arithmetic logic device
JPS58146949A (en) * 1982-02-26 1983-09-01 Nec Corp General logical circuit

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