JPS6446323A - Analog/digital converter - Google Patents

Analog/digital converter

Info

Publication number
JPS6446323A
JPS6446323A JP20327087A JP20327087A JPS6446323A JP S6446323 A JPS6446323 A JP S6446323A JP 20327087 A JP20327087 A JP 20327087A JP 20327087 A JP20327087 A JP 20327087A JP S6446323 A JPS6446323 A JP S6446323A
Authority
JP
Japan
Prior art keywords
bit
inversion amplifier
digital signals
amplifier circuit
analog
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20327087A
Other languages
Japanese (ja)
Inventor
Osamu Fujita
Tsuneo Tsukahara
Takeshi Ogura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP20327087A priority Critical patent/JPS6446323A/en
Publication of JPS6446323A publication Critical patent/JPS6446323A/en
Pending legal-status Critical Current

Links

Landscapes

  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE:To prevent a malfunction from being generated, by outputting an output voltage to another inversion amplifier circuit based on a digital signal obtained from an inversion amplifier circuit. CONSTITUTION:First, second...n-th bit digital signal output terminals T1, T2,...Tn which output first, second...n-th bit digital signals representing the contents of the first, second...n-th bits of binary coded digital signals are derived from the output terminals of the inversion amplifier circuits for first, second...n-th bit. Also, an input circuit Gj for j-th bit (j=1, 2...n) outputs the output voltage Vj to the inversion amplifier circuit Aj for j-th bit based on (j+1)-th, (j+2)-th...n- th bit digital signals obtained from the inversion amplifier circuits Aj+1, Aj+2...An for (j+1)-th, (j+2)-th...n-th bit. In such a way, the malfunction can be prevented from being generated.
JP20327087A 1987-08-14 1987-08-14 Analog/digital converter Pending JPS6446323A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20327087A JPS6446323A (en) 1987-08-14 1987-08-14 Analog/digital converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20327087A JPS6446323A (en) 1987-08-14 1987-08-14 Analog/digital converter

Publications (1)

Publication Number Publication Date
JPS6446323A true JPS6446323A (en) 1989-02-20

Family

ID=16471264

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20327087A Pending JPS6446323A (en) 1987-08-14 1987-08-14 Analog/digital converter

Country Status (1)

Country Link
JP (1) JPS6446323A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11713503B2 (en) 2011-12-23 2023-08-01 Hong Kong Baptist University Sapphire coated substrate with a flexible, anti-scratch and multi-layer coating

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11713503B2 (en) 2011-12-23 2023-08-01 Hong Kong Baptist University Sapphire coated substrate with a flexible, anti-scratch and multi-layer coating

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