JPS58146949A - General logical circuit - Google Patents

Abstract

PURPOSE:To utilize the titled circuit as a means for simulation or one custom LSI, by controlling the whole circuit on the basis of a starting signal from the external, and sending an end signal to the external at the completion of the processing. CONSTITUTION:Data applied from the external are applied to a control part 7 through a bus buffer 1 and a multiplexer 2 and stored in a register specified by the control part 7. Receiving a starting signal, the control part 7 applies the block No. to a decoder memory 4 and a gate selection memory 6. The decoder memory 4 outputs the contents of an input applied to the address on the basis of a bit pattern of the block. A gate memory 5 executes logical operation applied from the gate selection memory 6 in accordance with bits. The operated result of the memory 5 is sent to a register specified by the control part 7 and stored in the register.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a general-purpose logic circuit that can be used as a semi-real of a custom LSI or as a custom L8I.

With the spread of custom L8I, there has been a growing movement to realize logic circuit diagrams written by users using gate circuits using just 11 ICs.
In order to achieve this goal, thorough preparations are required, and there are many cases of second-guessing.

In order to promote custom LSI, custom LSI
Before converting into a circuit, a tool is needed to simulate the realized circuit diagram in some way.

Alternatively, it is desired to realize '&IC so that it can be realized in a custom L8I and the nine logic can be rewritten.

The purpose of the present invention is to meet these demands, and also serves as a tool for simulation.Here, we will first explain the principle of a general-purpose logic circuit.

FIG. 1 is a logic circuit diagram of a 4-bit full adder that is being implemented as a custom L8I.

In general-purpose logic circuits, when a circuit diagram is given, it is attempted to realize the circuit diagram according to the signal propagation time. In the logic circuit diagram shown in Figure 1, the maximum number of gate stages through which signals are transmitted is 4, so in a general-purpose logic circuit, the realization of each level of the 0th order is attempted for these four levels. Then, the number of input and output lines for that level is determined. In this case, it is assumed that the range that can be achieved by - operations is 8 for input lines and 4 or less for output lines.

For the next few moments, I will explain what pairs of inputs and outputs should be selected when simulating circuits at each level. Consider implementing the first rail circuit. Here, the input is Co,
A4 to Al. Since there are 9 Bl to B4O, I 1 = (C
O, Al to A3°B1~B3),! 2=(Mu4.B4)
It is divided into two groups If and I2. In a general-purpose logic circuit, when a signal is obtained from a set, it is assumed that up to four logical formulas can be realized using all or some of the signals of this set, and the value of the logical formula is the first half of a certain set. Alternatively, it can be used as an element in the latter half. At this time,
It is assumed that the original signal remains in the second half or the first half where no value is received.

Below, this will be represented by *. Also, Δ is assumed to be indefinite.

At level l, it can be realized by dividing into three operations. That is, from engineering 1, the first half of Jl is J1 = (Jl = CO, j
2=AI+81. I3-AI・B1. I4-mu2+B2
．． *, *, *, * ), the second half of 11, Jl = (*, *, *, *, j5 = A2 - B2.j6
=A3+B3. j7=A3・B3. Δ), I
2, we realize the first half of I2, J2=(j8=A4+B4.I9-M4・B4.Δ, Δ, *, *, *, *).

In preparation for level 2, the signals in the set are swapped.The swap also allows you to receive the same set of signals as the previous one and put them in the first or second half of some other set in any order. . At this time, the part where the signal did not come in remains as it is. Tubezu, J 1' from Jl
= (I5. I6. I7.Δ.

*, *, *, *＞, From I2, J1'=(*, *
, 31:.

*, I9. Δ, △, △), then J from 11'
Create 1 = (*, *, *, *, I5.I6. I7.I9). As a result, J 1 = (jl, I2. I3.
I4. I5. I6゜I7. I9), J2=(I8.
I9. Δ, Δ, Δ, Δ, Δ.

Δ).

Next KJ1. Level 2 is realized using J2. At level 2, tli is divided into seven operations, that is, 1 = (kl, 2. △, △, *, *.

* , * ), 1 = (*, *, *, *, 3. and 4.
5. Δ).

K2=(k6. to 7. to 8. to 9.*,*,*,*)
, to 3=(klo, kll, kx2.kla, *, *,
*, :t-), ni4= (kl5.kl6.kl7.k
l8. l *, *, *) by I2, 3=(*, l
*, l kl4. Δ, Δ.

△, △), 4=(*, *, *, *, kl9.
Δ, △.

△, △). As a result, K1=(k
l, k2. △, Δ, k3. k4. k5. Δ)
, K2=(k6゜k7. kg, kg, △, △, △
, Δ), to 3=(klo.

kll, kl2. kl3. kl4. Δ, Δ, Δ), ni4=(kl5゜kl6.kl7.kl8.kl9.△,
△, △) are obtained.

Next, K1. 2. 3. Level 3 is realized using 4. Some of the level 2 outputs do not pass through KIIi and level 3 and are input to level 4, but in a general-purpose logic circuit, it is made to look like there is a single-handed AND gate on the line, and a level 3 output signal is created. 6 For example, k5
Although it is an input to Fi level 4, it is made to look like there is an AND gate and a signal of t4=tS is created. Divided into Fi4 at level 3, that is, Kl! vL
1=(tl, A2゜ts, A4.*, *, *, *)
, by 2, L1=(*,*.

*, *, ts, ts, △, Δ), from 3, L2=
C17゜tS, Δ, Δ, *, *, *, *), from 4 to B2-(*.

*, *, *, A9. Δ, Δ, Δ).

Finally, perform level 4 actual using Ll and B2,
At level 3, we will divide it into two parts. That is, M1 from Ll
=(Σ1.Σ2.Σ3.Δ, *, *, *.

(ne) is obtained from B2 to obtain the Ml value (Δ, Δ, Δ, Δ, Σ4.C4゜*, n). ．Σ3゜Σ4.
*, *, *, *), M1'=(*, *, *, *, C4°Δ, Δ, Δ) are obtained. As a result, M1' has (Σ1゜Σ
2. Σ3. Σ4. C4, heme Δ) is obtained.

Next, consider realizing conversion from one set to another using a 16×4 bit memory element and MND, NAND, IOR, and NlOR gates. As an example, II=(Co,
A1. A2. Mu3. B1. B2. B3. △), J
1 = (jl = cO, j2 = Al + 81.
2. A3 is the address KFiBI of the second memory element,
B2. B3.・The output of the first memory element and the second
Separate KAND and NA memory elements depending on bits
It is assumed that it is an input to the gate of ND, NOR or NROR. The set of Jl is jl=cO, j2=A1 ・B
1. j3=A1・B1. It can be expressed as j4=4=·B2. Therefore, in the first memory element, when the address KCO is given, the first bit of the output becomes true, and when the address KCO is given, the second bit of the output becomes true. When AI is given to the address so that it is true, when A2 is given to the address so that the third bit of the output is true,
The second part writes the bit pattern so that the fourth bit of the output is true and the other parts are false.
The figure is a diagram showing an example when a bit pattern is written into the first memory element when true is set to 1, false is set to 0, and the first output is set to 81. FIG. 3 is a diagram showing an example of a bit pattern for the second memory element when the first output is T1. Furthermore, in Figure 4, the outputs of Sl and T1 are inputs to an AND gate, the outputs of 82 and T2 are inputs to another AND gate, the outputs of 83 and T3 are inputs to a NAND gate, and the outputs of 84 and T4 are inputs to a NAND gate. If the output is further input to another AND gate, the output of the gate is jl.

A2.13. It is a block diagram showing the principle of the present invention showing an example of A4 itself.

Generally logic gates (i.e. iN D , NAND,
pn.

In a logic circuit composed of NOR, IOR, NPCOR, and input inversion), conversion from one set to another H116 x 2 memory elements of 4 bits, ND, NA
ND, IOR, N1? Since it can be proven that it can be realized using an OR gate, the conversion from one set to another and the reversal of signals can all be realized by the method mentioned above. However, it is uneconomical and inflexible to provide such an element for every set of transformations, so the selection of memory blocks and gates may depend on which set of transformations is being performed. It is desirable to have hardware that can do this, and this is the general-purpose logic circuit of the present invention.

Therefore, it is desirable to select 4 large-capacity memory elements, divide them into blocks of 16 addresses each, and allocate one block for each conversion. That is, write #i and the bit pattern for the conversion assigned to it in a block, and when performing conversion, select the block, specify one address in that block by the input signal from the set, and write its contents. to appear. This allows multiple conversions to be performed with one memory element. Also, the output of the memory element is subjected to logical operations on a bit-by-bit basis, and one method for this is as follows.
AND, NAND, IOR, Nl! There is a method of preparing i0R gates and selecting one of them. Fourth
In the case of the figure, two memory elements KFi were considered, but when realizing a large-scale general-purpose logic circuit, the number of memory elements used Kti increases, and the number of inputs to the gate circuit increases. When the number of inputs increases in this way, many gate circuits are required, which is not economical. Therefore, it is better to implement this logic in memory. That is, as shown in FIG. 5, MND, N
The logic of AND, IOR, and NBOR is written in advance, and the operation to be performed is given to the outside, and the result of the logical operation is given by T1 and 81. This is called a gate memory and provides the same function as the gate circuit of FIG.

For example, even when there are eight memory elements,
The same can be achieved by increasing the capacity of the memory that implements the gate.

The general-purpose logic circuit of the present invention includes a round pass buffer that exchanges input/output data with the outside, a multiplexer that multiplexes data from the nozzle buffer and data from a gate memory (described later), and a A register set for storing data, a decode memory that decodes the data based on the data from the register, a gate memory that performs bitwise logical operations on the output of the decode memory, and a variety of logical operations. selects the gate selection memory that provides the input data, selects the register that should input data from the multiprouser, selects the register that should be input to the decode memory, controls the path buffer and multiplexer, and controls the decode memory and gate. It is composed of a control section that specifies the processing number in the selection memory, performs overall control based on a start signal from the outside, and sends an end signal to the outside upon completion of the processing.

FIG. 6 is a block diagram showing one embodiment of the present invention. In the figure, 1Fi path buffer, 2#i multiplexer, 3 is a register set, 4 is a decode memory, 5 is a gate memory, 6 is a gate selection memory, and 7 is a control section. The path buffer 1 exchanges input/output data with the outside. At this time, the direction in which the data flows is controlled by the control unit 7. Input data is sent from the outside to the general-purpose logic circuit, and output data is sent from the general-purpose logic circuit to the outside. Data flows externally. Multiplexer 2 multiplexes data from path buffer 1 or data from decode memory 4. Which data to select is controlled by the control unit 7. That is, data from buffer 1 is selected when processing is started, and data from decode memory 5 is selected during processing. Also, the control unit 7K
There is a message for Fi control, in which K can externally write information about which registers are used as inputs to the decode memory and which registers are used as outputs from the decode memory as processing progresses. In the case of data from the pass buffer 1, the data input to the pass buffer IK passes through the multi-break f2, and in the case of data from the decode memory 4, the data from the gate memory 5 passes through the multi-break f2. , the output of the gate memory 5 is given to the upper and lower multiplexers, respectively. That is, the same is true when selecting the outputs Fi of the upper and lower multiplexers and the data from the gate memory 5 side. The output from multiplexer 2 is written to any register in register set 4.

The control unit 7 determines which register to write into. If data to be written into the register is provided from outside, the data is written into the register specified by the control unit 7.

When the data to be written to the register is given from the gate memory 5, the control @7 not only specifies the register, but also specifies whether it is in the upper half or the lower half. The specified hand of the specified register is written based on the specified register. The output of a certain register is given to decode memory 4. A register to provide an output to the decode memory 4 is provided by the control section 7. The decode memory 4 consists of several memory elements (two memory elements in the figure).
) The address of a memory element is given the output of a register, but the memory element outputs the contents of that address. The output of the memory element becomes the input to the gate memory 5. Although the gate memory 5Fi is divided into several parts (
In the figure, the output of each memosa memory element (4) in the first part KI/i becomes the input. The gate selection memory 6 for the gate memory 5 performs logical operations AND, NAND, and EOR.

Which gate of NBOR should be selected is given for each gate memory 50 section. Each part of gate memory 5 performs a specified logical operation on the input from each memory element in decode memory 4 based on instructions from gate selection memory 6. This result is sent to multiplexer 2. The gate selection memory 6 specifies logical operations in each part of the gate memory 5 based on instructions from the control section 7.

The memory element in the decode memory 4 has a larger capacity than that described in the previous example, and is designed to be able to write a plurality of bit patterns used when converting from one set to another. This bit pattern can be written externally. Further, the control unit 7 determines which bit pattern to use to indicate conversion from which set to which set.
shows.

The control unit 7 is provided with an external command to determine which register gate selection memory 6 is to perform a logical operation on the output of each memory element when converting from one set to another according to the processing. However, this can also be written from outside. An example of a 4-bit full adder will now be explained. In the previous example, the conversion from one set to another was as follows: II-+Ji before, 11→J
1 later.

I2→Before J2, J1→Before J1', J2→After J1, J1
'→After Jl, 1 before J1→, 1 after J1→, 2 before J1→
Before.

J1→3 before, Jl→4 before, J2→3 after, J2→4 after, 1→L1 before, 2→L1 after, 3→L2 before.

K3 → after L2, LX → before M1, L2 → after M1, Ml → M
Before l', after Ml→Ml', these bit patterns are written by dividing the memory element into blocks of 16 addresses. In which block this is written is given to the control unit 7. Also, the logical operations used in these conversions, for example, AND, A before
The control unit 7 divides the gate selection memory 6 into blocks of 27 addresses and writes codes indicating ND, NAND, and AND when the block number is the same as that of the memory element.
The register numbers are given to 11 to M1'.

Next, the operation of the general-purpose logic circuit will be explained. When data is supplied from the outside, it is stored in a register that is specified by the control unit 7 through a path buffer 1° multiplexer 2. Next, when a start signal is given to the control unit 7 from the outside, the control unit 7 gives the register to be output to the decode memory 4 to the register set, and the block number to the decode memory 4 and the gate selection memory 6. . The decode memory 4 outputs the contents corresponding to the input given to the address based on the bit pattern in the block. The gate memory 5 performs bitwise operations according to the logical operations given from the gate selection memory 6. The result Fi is sent to the register designated by the control unit 7 and stored there. In the case of the previous 4-bit adder, the operation 11→J1 is performed, resulting in 9 times. Next, in order to perform the operation after II→J1, control section 7Fi
The register to be outputted to the decode memory 4 is designated, and a block number is given to the decode memory and gate selection memory. Then, it executes this until the last operation is performed, and when it is finished, it sends a termination signal to the outside,
Output data from the path buffer.

For the sake of simplicity, the explanation so far has been based on the case where one operation requires eight human power and four outputs, but this can be realized in any case.

For example, in the case of 32 human power and 16 outputs, this can be similarly achieved by using 8 memory elements.

[Brief explanation of the drawing]

Figure 1 is a diagram of a 4-bit full adder, Figures 2 and 3 are diagrams showing examples of bit patterns of a 4-bit full adder to be written to a general-purpose logic circuit, and Figure 4 shows the principle of a general-purpose logic circuit. The block diagram shown in FIG. 5 is a diagram of a rounding memory realizing a gate, and FIG. 6 is a block diagram showing an embodiment of a general-purpose logic circuit of the present invention. 1, Pass buffer 2, Multiplexer 3, Register set 4, Decode memory 5, Gate memory 6, Gate selection memory 7% Control Department Representative Patent Attorney Susumu Hakubi figure

Claims (1)

[Claims] As a rounding means for realizing logical functions, there is a path buffer for exchanging input/output data with the outside, a multiplexer for multiplexing data from the path buffer and data from a gate memory (described later), and a multiplexer for multiplexing data from the multiplexer. A register set consisting of a set of registers for storage, a decode memory that decodes data based on the data from the register, a gate memory that performs bitwise logical operations on the output of the decode memory, and the logical operations. The gate selection memory that gives the type of data and the internal information stored in the control unit select the register to which the data from the multiprouser should be input from the register set, and select the register to be input to the decode memory. It controls the path buffer and multiplexer from the register set, specifies the processing number in the decode memory and gate selection memory, and performs overall control based on the start signal from the outside. 1. A general-purpose logic circuit characterized by comprising a control section that sends a termination signal to the outside.