JP3201423B2 - Memory test equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory test apparatus, and more particularly, to a test of a continuous flash write operation of a memory under test (hereinafter referred to as an MUT).

[0002]

2. Description of the Related Art In an image memory, an operation mode called a flash (write) mode in which, for example, 4-bit data stored in a built-in data register (color register) is simultaneously written into one row of memory cells of a predetermined row address. There is. Array of MUT is, for example, the row address signal A ₀ to A ₇ and the column address signals A ₈ to A ₁₅ as shown in FIG. 4 (each 8 bits) are input, 0-2
Assuming a 256 × 256 × 4 bit configuration by stacking four layers (sheets) of 256 × 256 bit memory chips having a row address of address 55 and a column address of addresses 0 to 255, 256x4 in a row
Data of a 4-bit configuration is simultaneously written to the memory cells.

Further, a 4-bit mask register is incorporated in the image memory, for example, to store mask data.
When rewriting data in one row of memory cells in the same row address of each chip in flash write mode, either the data in this mask register or the input mask data
With the mask data (4 bits), a specific bit in the 4-bit data is masked, and rewriting of the bit can be prevented.

FIG. 5 shows a conventional memory test apparatus for an MUT having such a flash (write) mode.
This will be described with reference to FIG. Address signal SA, mask data signal SMD, data signal SD from pattern generator 1
And the MUT control signal SC1 is supplied to the MUT2, and the address signal SA, the mask data signal SMD, the data signal S
D and the control signal SC2 are supplied to the expected value generator 3, respectively. The read RD read from the MUT 2 and the expected value KD output from the expected value generator 3 are respectively input to the logical comparator 4 and logically compared, and the MUT is tested.

A pattern generator 1 generates an address signal SA and a mask data signal SMD.
a, a data generator 1b for generating a data signal SD,
M that generates MUT control signal (including clock) SC1
It comprises a UT control signal generator 1c, a control signal generator 1d for generating a control signal SC2 for the expected value generator 3, and a sequence controller 1e for controlling the sequence of these units.

The configuration of the expected value generator 3 will be described with reference to FIG. The buffer memory 5 has a capacity equal to or larger than that of the MUT 2. Therefore, it has memory chips (four in the example in the figure) stacked by a number equal to or greater than the data bit width of the MUT 2. An address signal SA (for example, 8 bits each for a row address and a column address) is applied to an address input terminal A of the buffer memory 5. For example, 4
The bit-structured data signal SD is input to the data register 6 and the multiplexer 7, and the output of the data register 6 is input to the multiplexers 7 and 8, respectively. In the multiplexer 7, one of the input data signal SD at a certain time and the output of the data register 6 is selected and applied to the data input terminal D of the buffer memory 5.

For example, a 4-bit mask data signal SMD
Is input to a mask register (for example, a 4-bit configuration) 9 and a multiplexer 10, and the output of the mask register 9 is input to the multiplexer 10. In the multiplexer 10, one of the input mask data signal SMD at a certain time and the output of the mask register 9 is selected and applied to one input terminal of each of the AND gate groups 11 and 12.
The control signal SC2 is supplied to one input terminal of the data register 6, the mask register 9, the multiplexers 7 and 10, and the AND gate groups 11 and 12. AND gate group 1
Numerals 1 and 12 are composed of AND gates of the same number as the data bit width (for example, 4 bits), and their outputs are respectively input to the write enable signal input terminal WE of the buffer memory 5 and the select signal input terminal S of the multiplexer 8.

Since the output of the AND gate group 11 corresponding to the L logic bit of the mask data output from the multiplexer 10 has the L logic, the chip corresponding to the buffer memory 5 is not supplied with the H logic write enable signal. , The rewriting of that bit is prohibited. Note that the equivalent of the data register 6 and the mask register 9 is the MUT
2 built in.

Since the buffer memory 5 is composed of a normal memory unlike the MUT 2, a flash (write)
Does not have write function in mode. At the same time that the MUT 2 writes data in the flash write mode, the same data is stored in the data register 6 and the MUT 2 is read immediately after that. At this time, in the multiplexer 8, the data stored in the data register 6 is selected as the unmasked bit and the read data of the buffer memory 5 is selected as the bit to be masked by the output of the AND gate 12.

In a state in which the quality of the flash write of the MUT 2 is tested, data (4 bits) is read from the MUT 2 in each test cycle, but the data is read from the buffer memory 5 in the first half of one test cycle. And write in the second half. This gives M
In the process of testing the success or failure of the flash write of the UT 2, the contents of the data register 6 can be written to the buffer memory 5 with the mask applied, so that the contents of the MUT 2 and the contents of the buffer memory 5 can be matched. .

The mask data signal SMD is generated by the address generator 1a in FIG.
2 and the expected value generator 3, but may be generated by the data generator 1b and supplied through a data bus.

[0012]

In a conventional test apparatus incorporating a data register 6 and a mask register 9 in a buffer memory system for emulating the operation of the MUT 2, the MU
When the flash write is performed once by T2, the expected value KD synthesized with the data of the buffer memory 5, the data register 6, and the mask register 9 and the read data RD of the MUT 2 are logically written to the area of one row address. The next flash write could not be executed unless the comparison was performed by the comparator 4.

However, in the actual use state of the MUT 2, the flash write is not limited to the memory cells for one row address.
Generally, writing is continuously performed on memory cells for a plurality of row addresses for each row address. Therefore, the test apparatus it is desirable to be able to test the quality of continuous flashlight operation MUT2. However, the conventional apparatus has a problem that a continuous flash write operation test cannot be performed as described above. An object of the present invention is to solve this problem and to enable a continuous flash write operation test.

[0014]

According to the present invention, the expected value generator is constituted by an array of M × N (M = the number of words, N = the number of data bits) using a plurality of memories. A buffer memory having a memory capacity equivalent to that of the MUT, a data register in which a data register in the MUT can write the data signal in synchronization with an operation of writing the data signal, an output of the data address, and the generation of the pattern A first multiplexer for switching a data signal input from a memory device and supplying the data signal to a data input terminal of the buffer memory; and a mask register in the MUT for synchronizing the operation of writing the mask data signal with the mask data signal. A writable mask register, an output of the mask register, and a mask data signal input from the pattern generator. It comprises a switchable second multiplexer and the same number of AND gates as the data bit width of the MUT, and one input of each of the AND gates has a one-to-one correspondence with each bit of the mask data of the second multiplexer output. A buffer memory write command from the pattern generator is commonly input to the other input, and an AND gate group capable of inhibiting writing of the buffer memory in bit units and the address signals (row, Arbitrarily rearranges the row and column address bits from the column address, and supplies the row address bits to the address input terminal of the buffer memory; and the decode address in the column address of the output of the address selector. • Remaining address bits excluding bits (counter address And a counter that performs an increment operation within one flash write cycle of the MUT, and switches between the counter address bit and the counter output bit to be supplied to an address input terminal of the buffer memory. A third multiplexer, a decoder for decoding a decode address in a column address of the address selector output, and selecting a predetermined memory from among a plurality of memories constituting the buffer memory, and a decoder for synchronizing with a flash write operation of the MUT. The buffer memory, the counter, and the third multiplexer are controlled so that the buffer memory has the same data amount as the data amount of one row address area accessed by one flash write operation of the MUT. Write multiple memories all at once The includes a controller for writing made to perform a plurality of times.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an expected value generator 3 used in a memory test apparatus according to the present invention, in which parts corresponding to those in FIG. In this example, the MUT 2 has a row address and a column address, each having 8 bits (256 words) and a data width of 4 bits, and the buffer memory 5 is a 16-bit memory having a 1-bit data width × 4 layers, and is composed of 64 in total. .

Before describing the operation, each functional block will be briefly described. Functions of multiplexers 7 and 10, data register 6, mask register 9, and AND gate group 12
The operation is the same as the conventional one shown in FIG. The multiplexer 7 is switched so as to select data on the data register 6 side by a flash write instruction from the pattern generator (PG) 1. The multiplexer 10 is switched so as to select the data on the mask register 9 side by a mask data switching instruction from the PG1. The data register 6 loads data by a data load instruction from PG1.
The mask register 9 loads a mask data signal SMD in response to a mask data load instruction from PG1.

The AND gate group 12 is composed of AND gates of the same number (four in this example) as the data bit width of the buffer memory 5, and one of the inputs is one-to-one with the mask data (output of the multiplexer 10) bit. The output of the OR gate 21 is connected to the other, and the other is connected to the other. Buffer OR of memory write instruction S ₂ from the buffer memory write instruction S ₁ and PG1 from the OR gate 21 in the controller 22 is taken.

The address selector 23 selects the address signal SA (row, column address) from the PG1 shown in FIG.
As shown in (1), the column address and the row address are formatted and output in order from the LSB (lower bit) side. In this example, the 8-bit column address is divided into a 4-bit decode address and a 4-bit counter address.

The buffer memory 5 is composed of 64 16 × 4 = 64 memories having a 1-bit data width as described above.
It has a memory capacity of 256 × 256 × 4 bits equivalent to T2, is arranged in 16 columns × 4 layers, and has a 4-bit decode /
The address is decoded by the decoder 24, and one of the 16 columns is read.
The column is selected. Address input terminal A for 64 memories
, A row address (8 bits) and a counter address (4 bits) are commonly applied.

The controller 22 receives the same command as the flash write command for the MUT 2 from the pattern generator 1 and stores it in the buffer memory 5 16 times in one flash write cycle of the MUT 2 as shown in FIG. (16 times since the address bit is 4 bits) The write operation is controlled. The counter 25 is composed of 4 bits, and is controlled from 0 to 15 (# 0 to #F in hexadecimal) in one flash write cycle under the control of the controller 22.
The increment (+1) operation up to is performed. The multiplexer 26 switches between the counter address bits excluding the decode address bits in the column addresses shown in FIG.

An OR gate group 27 composed of 16 OR gates has one of the inputs which is one-to-one with the output of the decoder 24.
And the other is commonly connected to the output of the controller 22. As a result, the buffer memory 5 can write to all 64 memories by a single write instruction in a flash write cycle. In this apparatus, similarly to the related art, when the test of the MUT 2 is started and the data is written to the MUT 2, the same data is written to the buffer memory, and when the data is read from the MUT 2, the data is read from the buffer memory 5; The test is performed by comparing this data with the read data RD from the MUT 2 as the expected value KD.

MUT2 is flash write data SD
Write the same data to the data register 6 of the present device, and similarly write the same data to the mask register 9 of the present device when writing the mask data SMD to the internal mask register. As shown in FIG. 3, when the MUT 2 executes a flash write,
The buffer memory 5 has 64 buffers under the control of the controller 22.
The operation of writing to one memory at a time is performed 16 times, and
Data corresponding to 4 × 16 = 1024 bits, that is, data corresponding to 256 × 4 = 1024 bits for one row address of the MUT 2 is written. As a result, the data in the MUT 2 always matches the data in the buffer memory 5 even immediately after the MUT 2 executes the flash write, so that a continuous flash write operation on the MUT 2 can be performed. After the end of the continuous flash write, data for a plurality of row addresses written from the MUT 2 and the buffer memory 5 can be continuously read and compared.

[0023]

As described above, according to the present invention, M
An operation of writing all of the plurality of memories constituting the buffer memory 5 in the expected value generator 3 at a time to the same data amount as the area of one row address accessed in one flash write operation of the UT 2 Is performed a plurality of times, and writing can be performed. As a result, even immediately after the MUT 2 executes the flash write, the data in the MUT 2 and the data in the buffer memory 5 always match, so that the continuous flash write to the MUT 2 can be performed.

After the continuous flash write is completed, a continuous flash write operation test is performed by continuously reading and comparing data of a plurality of row addresses written in both, that is, the same conditions as in the actual use state of the MUT. Can be tested in

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of an expected value generator used in a memory test device of the present invention.

FIG. 2 is a diagram showing input / output data of an address selector 23 in FIG. 1;

FIG. 3 is an operation waveform diagram of a main part of FIG. 1;

FIG. 4 is a diagram showing a configuration example of a cell array in a memory under test (MUT).

FIG. 5 is a block diagram showing an outline of a configuration of a conventional and a memory test apparatus of the present invention.

FIG. 6 is a block diagram of a conventional expected value generator used in a memory test apparatus.

Claims (1)

(57) [Claims] An expected value generator, an expected value output from the expected value generator, and a memory under test (hereinafter referred to as MUT).
A logical comparator for logically comparing the data read from
A memory test apparatus comprising: a pattern generator that supplies an address signal, a data signal, and a mask data signal to the MUT and the expected value generator in parallel and supplies a control signal to each of the MUT and the expected value generator; M × N using the memory of
(M = number of words, N = number of data bits), a buffer memory having a memory capacity at least equal to that of the MUT, and a data register in the MUT in synchronization with the operation of writing the data signal, A data register capable of writing the data signal, a first multiplexer for switching an output of the data register and a data signal input from the pattern generator and supplying the data signal to a data input terminal of the buffer memory, and a mask in the MUT A register capable of writing the mask data signal in synchronization with the operation of writing the mask data signal by the register; and a mask register capable of switching between the output of the mask register and the mask data signal input from the pattern generator. Consists of two multiplexers and the same number of AND gates as the data bit width of the MUT Is the to one input of each of these AND gates second
Each bit of the mask data of the multiplexer output is 1
A buffer memory write command from the pattern generator is commonly input to the other input, and an AND gate group capable of inhibiting writing of the buffer memory in bit units; An address selector for arbitrarily rearranging row and column address bits from (row, column address) and supplying the row address bits to an address input terminal of the buffer memory; Has the same number of bits as the remaining address bits (counter address bits) excluding the decode address bits of
A counter that performs an increment operation within one flash write cycle of the MUT, a third multiplexer that switches between the counter address bit and the counter output bit and supplies the counter address bit to an address input terminal of the buffer memory, and the address selector A decoder for decoding a decode address in an output column address and selecting a predetermined memory from among a plurality of memories constituting the buffer memory; and a buffer memory, a counter, and a By controlling the operation of the three multiplexers, the same data amount as the data amount of one row address area accessed by one flash write operation of the MUT is obtained.
A memory test apparatus, comprising: a controller for performing an operation of writing all of a plurality of memories constituting the buffer memory all at once a plurality of times and writing the data.