JPS6433949A - Wiring board for mounting semiconductor element - Google Patents

Wiring board for mounting semiconductor element

Info

Publication number
JPS6433949A
JPS6433949A JP18914187A JP18914187A JPS6433949A JP S6433949 A JPS6433949 A JP S6433949A JP 18914187 A JP18914187 A JP 18914187A JP 18914187 A JP18914187 A JP 18914187A JP S6433949 A JPS6433949 A JP S6433949A
Authority
JP
Japan
Prior art keywords
holes
insulating
wiring board
insulating layer
insulating layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18914187A
Other languages
Japanese (ja)
Inventor
Koichi Tsuyama
Masashi Isono
Toshiro Okamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Showa Denko Materials Co Ltd
Original Assignee
Hitachi Chemical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Chemical Co Ltd filed Critical Hitachi Chemical Co Ltd
Priority to JP18914187A priority Critical patent/JPS6433949A/en
Publication of JPS6433949A publication Critical patent/JPS6433949A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector

Landscapes

  • Insulated Metal Substrates For Printed Circuits (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To implement a relatively low cost and a large size and to obtain the wiring board having a highly reliable connecting part to a semiconductor element, by forming the wiring board comprising a metal plate, insulating layers and a conductor circuit, and forming the insulating layers, which comprise a first insulating layer, wherein through holes are provided, a rubber based material filled in the holes, and a resin based planar second insulating layer. CONSTITUTION:A wiring board comprises a metal plate 1, insulating layers and a conductor circuit 4. The insulating layers comprise a first insulating layer 21, in which through holes are provided, a rubber based material filled in said holes and a resin based planar second insulating layer 22. For example, a copper foil having a thickness of 25mum is compressed, heated and laminated on one surface of epoxy-resin impregnated glass cloth having a thickness of 50mum, and an insulating resin layer, on one surface of which copper is lined, is formed. A grid shaped material, in which holes each having one-side length of 10mm are formed, is separately formed by using a polyimide film having a thickness of 50mum. A silicone-rubber bonding agent is applied on the metal plate having the of 1mm. Said grid shaped material of polyimide film is overlapped thereon. Said bonding agent is applied thereon. Then, said insulating resin layer, on one-surface of which the copper is lined, is laminated. Pressure is applied and the materials are heated. Thus a unitary body is provided. Thin, the copper foil on the surface is selectively etched, and the conductor circuit 4 is formed.
JP18914187A 1987-07-29 1987-07-29 Wiring board for mounting semiconductor element Pending JPS6433949A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18914187A JPS6433949A (en) 1987-07-29 1987-07-29 Wiring board for mounting semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18914187A JPS6433949A (en) 1987-07-29 1987-07-29 Wiring board for mounting semiconductor element

Publications (1)

Publication Number Publication Date
JPS6433949A true JPS6433949A (en) 1989-02-03

Family

ID=16236099

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18914187A Pending JPS6433949A (en) 1987-07-29 1987-07-29 Wiring board for mounting semiconductor element

Country Status (1)

Country Link
JP (1) JPS6433949A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5402003A (en) * 1993-11-12 1995-03-28 Trw Inc. Low dielectric constant interconnect for multichip modules
US5895956A (en) * 1994-12-08 1999-04-20 Kabushiki Kaisha Toshiba Semiconductor memory device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5402003A (en) * 1993-11-12 1995-03-28 Trw Inc. Low dielectric constant interconnect for multichip modules
US5895956A (en) * 1994-12-08 1999-04-20 Kabushiki Kaisha Toshiba Semiconductor memory device
US6130461A (en) * 1994-12-08 2000-10-10 Kabushiki Kaisha Toshiba Semiconductor memory device
US6342408B1 (en) 1994-12-08 2002-01-29 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor memory device
US6545323B2 (en) 1994-12-08 2003-04-08 Kabushiki Kaisha Toshiba Semiconductor memory device including a pair of MOS transistors forming a detection circuit

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