JPS6433644A - Control system for video memory - Google Patents

Control system for video memory

Info

Publication number
JPS6433644A
JPS6433644A JP62188945A JP18894587A JPS6433644A JP S6433644 A JPS6433644 A JP S6433644A JP 62188945 A JP62188945 A JP 62188945A JP 18894587 A JP18894587 A JP 18894587A JP S6433644 A JPS6433644 A JP S6433644A
Authority
JP
Japan
Prior art keywords
memory
page
data
signal
sheet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62188945A
Other languages
Japanese (ja)
Inventor
Katsumi Nagata
Shuichi Nakakawaji
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP62188945A priority Critical patent/JPS6433644A/en
Publication of JPS6433644A publication Critical patent/JPS6433644A/en
Pending legal-status Critical Current

Links

Landscapes

  • Record Information Processing For Printing (AREA)
  • Storing Facsimile Image Data (AREA)
  • Dot-Matrix Printers And Others (AREA)

Abstract

PURPOSE:To effectively increase the printing speed by securing such a constitution where all data stored in a memory is always cleared in both single sheet or multi-sheet printing modes when a reading action is through with a relevant page and it is not required to write an erasion signal (zero data) into the entire area of a single page when the picture data on the next page is written. CONSTITUTION:A write control signal Ws is outputted from a CPU in a reading cycle right before a writing action of the picture data on the next page in both single sheet and multi-sheet print modes of each page. An AND is secured between the signal Ws and a write pulse signal WR via a gate circuit 5 and the signals are delivered toward a video memory 1 based on a read timing mode. Then the zero data is written into the memory 1 corresponding to the address which is read out in parallel with the reading action of the picture data. The data stored in said address are successively erased. Therefore all data are cleared in the memory 1 when the reading action is through with the relevant page in both print modes. Thus the effective and high-speed memory control is attained.
JP62188945A 1987-07-30 1987-07-30 Control system for video memory Pending JPS6433644A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62188945A JPS6433644A (en) 1987-07-30 1987-07-30 Control system for video memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62188945A JPS6433644A (en) 1987-07-30 1987-07-30 Control system for video memory

Publications (1)

Publication Number Publication Date
JPS6433644A true JPS6433644A (en) 1989-02-03

Family

ID=16232662

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62188945A Pending JPS6433644A (en) 1987-07-30 1987-07-30 Control system for video memory

Country Status (1)

Country Link
JP (1) JPS6433644A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012081733A (en) * 2010-09-16 2012-04-26 Ricoh Co Ltd Printer and method of controlling the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60134334A (en) * 1983-12-23 1985-07-17 Hitachi Ltd Printing controlling system
JPS61264379A (en) * 1985-05-20 1986-11-22 株式会社日立製作所 Memory circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60134334A (en) * 1983-12-23 1985-07-17 Hitachi Ltd Printing controlling system
JPS61264379A (en) * 1985-05-20 1986-11-22 株式会社日立製作所 Memory circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012081733A (en) * 2010-09-16 2012-04-26 Ricoh Co Ltd Printer and method of controlling the same

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