JPS6432650A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6432650A
JPS6432650A JP7801188A JP7801188A JPS6432650A JP S6432650 A JPS6432650 A JP S6432650A JP 7801188 A JP7801188 A JP 7801188A JP 7801188 A JP7801188 A JP 7801188A JP S6432650 A JPS6432650 A JP S6432650A
Authority
JP
Japan
Prior art keywords
insulating film
etching
onto
arrow
self
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7801188A
Other languages
Japanese (ja)
Other versions
JPH0573348B2 (en
Inventor
Takamitsu Kamiyama
Yoshifumi Kawamoto
Sadayuki Okudaira
Tokuo Kure
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP7801188A priority Critical patent/JPS6432650A/en
Publication of JPS6432650A publication Critical patent/JPS6432650A/en
Publication of JPH0573348B2 publication Critical patent/JPH0573348B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To form an insulating film having excellent characteristics in a self- alignment manner by shaping a second insulating film to the side sections of a first conductive film and an insulating film by using anisotropic etching and forming a second conductive film onto the whole surface. CONSTITUTION:The stratified pattern of an electrode wiring 2a and an insulating film 3a is shaped onto a desired substrate 1a, and an insulating film 3b is applied onto the whole surface. When the insulating film 3b is etched by using a dry etching method such as a reactive sputtering etching method, etching selectively progresses in the vertical direction (the arrow Y), and does not progress in the lateral direction (the arrow X). Consequently, when etching is stopped when the surface of the substrate 1a is exposed, the top face of the electrode wiring 2a can be coated with the insulating film 3a and a side face thereof with the insulating film 3b selectively in a self-alignment manner. Accordingly, a memory cell can be fined.
JP7801188A 1988-04-01 1988-04-01 Manufacture of semiconductor device Granted JPS6432650A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7801188A JPS6432650A (en) 1988-04-01 1988-04-01 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7801188A JPS6432650A (en) 1988-04-01 1988-04-01 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS6432650A true JPS6432650A (en) 1989-02-02
JPH0573348B2 JPH0573348B2 (en) 1993-10-14

Family

ID=13649849

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7801188A Granted JPS6432650A (en) 1988-04-01 1988-04-01 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6432650A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5444482A (en) * 1977-09-14 1979-04-07 Matsushita Electric Ind Co Ltd Mos type semiconductor device and its manufacture

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5444482A (en) * 1977-09-14 1979-04-07 Matsushita Electric Ind Co Ltd Mos type semiconductor device and its manufacture

Also Published As

Publication number Publication date
JPH0573348B2 (en) 1993-10-14

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