JPS6428749A - Monitor system for microcomputer normal operation - Google Patents

Monitor system for microcomputer normal operation

Info

Publication number
JPS6428749A
JPS6428749A JP62185076A JP18507687A JPS6428749A JP S6428749 A JPS6428749 A JP S6428749A JP 62185076 A JP62185076 A JP 62185076A JP 18507687 A JP18507687 A JP 18507687A JP S6428749 A JPS6428749 A JP S6428749A
Authority
JP
Japan
Prior art keywords
program
monitor
circuits
microcomputer
function levels
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62185076A
Other languages
Japanese (ja)
Inventor
Tadashi Mizuguchi
Katsunori Sugawara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
NEC Communication Systems Ltd
Original Assignee
NEC Corp
NEC Communication Systems Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, NEC Communication Systems Ltd filed Critical NEC Corp
Priority to JP62185076A priority Critical patent/JPS6428749A/en
Publication of JPS6428749A publication Critical patent/JPS6428749A/en
Pending legal-status Critical Current

Links

Landscapes

  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To monitor the normal operation in each function level of a program to easily detect an abnormal operation by providing plural monitor circuits corresponding to respective function levels of the program of a microcomputer and monitoring normalcy of the program by these monitor circuits. CONSTITUTION:A memory 3 consisting of a ROM incorporating the program and a work RAM, an input/output circuit 4, and monitor circuits 12-14 which monitor function levels 1-(n) of the program of a microcomputer 1 are connected to the microcomputer 1 by a bus 2. Control signals to reset counters corresponding to respective function levels are sent to decoders 5-7 of circuits 12-14. Counters 8-10 are reset by these control signals before exceeding a certain set value and do not send an alarm signal to an alarm detecting circuit 11. Normalcy in respective function levels of the program is monitored by circuits 12-14 to easily detect the abnormal operation of the program of the computer.
JP62185076A 1987-07-23 1987-07-23 Monitor system for microcomputer normal operation Pending JPS6428749A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62185076A JPS6428749A (en) 1987-07-23 1987-07-23 Monitor system for microcomputer normal operation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62185076A JPS6428749A (en) 1987-07-23 1987-07-23 Monitor system for microcomputer normal operation

Publications (1)

Publication Number Publication Date
JPS6428749A true JPS6428749A (en) 1989-01-31

Family

ID=16164397

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62185076A Pending JPS6428749A (en) 1987-07-23 1987-07-23 Monitor system for microcomputer normal operation

Country Status (1)

Country Link
JP (1) JPS6428749A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8155824B2 (en) 2008-02-04 2012-04-10 Denso Corporation Electronic control apparatus for vehicles, which is provided with plural microcomputers

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8155824B2 (en) 2008-02-04 2012-04-10 Denso Corporation Electronic control apparatus for vehicles, which is provided with plural microcomputers

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