JPS5723156A - Fault monitoring system of information processor - Google Patents

Fault monitoring system of information processor

Info

Publication number
JPS5723156A
JPS5723156A JP9682080A JP9682080A JPS5723156A JP S5723156 A JPS5723156 A JP S5723156A JP 9682080 A JP9682080 A JP 9682080A JP 9682080 A JP9682080 A JP 9682080A JP S5723156 A JPS5723156 A JP S5723156A
Authority
JP
Japan
Prior art keywords
output
input
information
controller
line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9682080A
Other languages
Japanese (ja)
Inventor
Shigehiro Funatsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP9682080A priority Critical patent/JPS5723156A/en
Publication of JPS5723156A publication Critical patent/JPS5723156A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To detect and diagnose easily a fault of an input and output control means, such as an input and output controller and an arithmetic controller, connected to a bus, by inputting a control signal driving a control circuit to a 1/N checking circuit and by monitoring its output. CONSTITUTION:Information is sent from one of input and output controllers 1'-1- 1'-N onto a bus line 3 via a two-way input and output line and the information is fetched by the other corresponding output and input controller. At this time, only one of signal lines 5-1-5-N which corresponds to the input and output controller having sent the information onto the bus line 3 is in output mode by receiving the command of information transmission. Signals of the signal lines 5-1 and 5-2-5-N are inputted to 1/N checking circuit 4. Then, the states of respective input signals are monitored by the output of an output line 6 to know whether an information processor is in normal operation or not.
JP9682080A 1980-07-17 1980-07-17 Fault monitoring system of information processor Pending JPS5723156A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9682080A JPS5723156A (en) 1980-07-17 1980-07-17 Fault monitoring system of information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9682080A JPS5723156A (en) 1980-07-17 1980-07-17 Fault monitoring system of information processor

Publications (1)

Publication Number Publication Date
JPS5723156A true JPS5723156A (en) 1982-02-06

Family

ID=14175207

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9682080A Pending JPS5723156A (en) 1980-07-17 1980-07-17 Fault monitoring system of information processor

Country Status (1)

Country Link
JP (1) JPS5723156A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0317498U (en) * 1989-06-30 1991-02-21

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0317498U (en) * 1989-06-30 1991-02-21

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