JPS5786925A - Malfunction detection system - Google Patents

Malfunction detection system

Info

Publication number
JPS5786925A
JPS5786925A JP55163018A JP16301880A JPS5786925A JP S5786925 A JPS5786925 A JP S5786925A JP 55163018 A JP55163018 A JP 55163018A JP 16301880 A JP16301880 A JP 16301880A JP S5786925 A JPS5786925 A JP S5786925A
Authority
JP
Japan
Prior art keywords
output
input
signal
sel
equipments
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55163018A
Other languages
Japanese (ja)
Inventor
Masao Sato
Fumio Hoshi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55163018A priority Critical patent/JPS5786925A/en
Publication of JPS5786925A publication Critical patent/JPS5786925A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To output a malfunction signal when two of peripheral equipments are in operation by using one check signal line and simple constitution by providing exclusive OR circuits to the peripheral equipments connected in series. CONSTITUTION:Input-output equipments 1, 2 and 3 are provided with exclusive OR circuits 10, 11 and 12. If the input-output equipment 1 is in operation, a selection signal SEL-A is a 1 and a signal 0 is applied to the other input line 16-1 at all times, so that a selective check signal SLCK-A is a 1. The SEL-B and SEL-C are normally 0s because they are not in operation. Therefore, the output of an inverter 14 in an input-output controller 4 is a 0 and if even one equipment is in operation, a fault check signal CKTMG is a 1, so that an AND circuit 15 outputs a 0. When the other input-output equipments operate, the inverter 14 outputs a 1, so that a signal ErO indicating an error occurrence state is outputted as a 1.
JP55163018A 1980-11-19 1980-11-19 Malfunction detection system Pending JPS5786925A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55163018A JPS5786925A (en) 1980-11-19 1980-11-19 Malfunction detection system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55163018A JPS5786925A (en) 1980-11-19 1980-11-19 Malfunction detection system

Publications (1)

Publication Number Publication Date
JPS5786925A true JPS5786925A (en) 1982-05-31

Family

ID=15765622

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55163018A Pending JPS5786925A (en) 1980-11-19 1980-11-19 Malfunction detection system

Country Status (1)

Country Link
JP (1) JPS5786925A (en)

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