JPS56108102A - Take-in system of relay state - Google Patents

Take-in system of relay state

Info

Publication number
JPS56108102A
JPS56108102A JP1010980A JP1010980A JPS56108102A JP S56108102 A JPS56108102 A JP S56108102A JP 1010980 A JP1010980 A JP 1010980A JP 1010980 A JP1010980 A JP 1010980A JP S56108102 A JPS56108102 A JP S56108102A
Authority
JP
Japan
Prior art keywords
output
state
circuit
relay
existence
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1010980A
Other languages
Japanese (ja)
Inventor
Hirohisa Hayakawa
Hideo Kanzaki
Tsuyoshi Mizoguchi
Hiroshi Sugisaka
Hironobu Watanabe
Noritoshi Fujii
Hiroaki Aotsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP1010980A priority Critical patent/JPS56108102A/en
Publication of JPS56108102A publication Critical patent/JPS56108102A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Testing And Monitoring For Control Systems (AREA)
  • Safety Devices In Control Systems (AREA)

Abstract

PURPOSE:To prevent the malfunction due to a simultaneous falut, by supplying the two state signals which originally cannot have the same state. CONSTITUTION:The circuits 7 and 8 supply the output ''1'' when one side of the input is ''1'' with the other side of ''0'' respectively. As either one of the circuits 7 and 8 is always ''1'' with the other set under ''0'' in the normal state, the relay state can be taken in by having a decision with a correspondence secured between the existence of output of the circuit 7 and the operation of the relay as well as between the existence of output of the circuit 8 and the nonoperation of the relay respectively. The logic circuit 9 delivers an output when both inputs mentioned above are ''0''. The existence of output of the circuit 9 means that the same state has been secured for the two inputs which originally cannot have the same state. As a result, the occurrence of some fault is decided to block the logic decision to be given by the outputs of the circuits 7 and 8. In such way, the malfunction due to a simultaneous fault can be prevented.
JP1010980A 1980-02-01 1980-02-01 Take-in system of relay state Pending JPS56108102A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1010980A JPS56108102A (en) 1980-02-01 1980-02-01 Take-in system of relay state

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1010980A JPS56108102A (en) 1980-02-01 1980-02-01 Take-in system of relay state

Publications (1)

Publication Number Publication Date
JPS56108102A true JPS56108102A (en) 1981-08-27

Family

ID=11741140

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1010980A Pending JPS56108102A (en) 1980-02-01 1980-02-01 Take-in system of relay state

Country Status (1)

Country Link
JP (1) JPS56108102A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6180301A (en) * 1984-09-28 1986-04-23 Hitachi Ltd Checking circuit of control output relay in control device
JPH0391704U (en) * 1989-12-29 1991-09-18

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6180301A (en) * 1984-09-28 1986-04-23 Hitachi Ltd Checking circuit of control output relay in control device
JPH0391704U (en) * 1989-12-29 1991-09-18

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