JPS5368065A - Exclusive logical sum circuit - Google Patents
Exclusive logical sum circuitInfo
- Publication number
- JPS5368065A JPS5368065A JP14322376A JP14322376A JPS5368065A JP S5368065 A JPS5368065 A JP S5368065A JP 14322376 A JP14322376 A JP 14322376A JP 14322376 A JP14322376 A JP 14322376A JP S5368065 A JPS5368065 A JP S5368065A
- Authority
- JP
- Japan
- Prior art keywords
- logical sum
- exclusive logical
- sum circuit
- circuit
- reverse
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
- H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
- H03K19/212—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical using bipolar transistors
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
Abstract
PURPOSE:To avoid occurrence of a DC pass between the adjacent circuits even though plural units of 2-input exclusive logical sum circuit are connected in parallel, by connecting the reverse-current preventing diode to the input terminal and also providing a bias circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14322376A JPS5368065A (en) | 1976-11-29 | 1976-11-29 | Exclusive logical sum circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14322376A JPS5368065A (en) | 1976-11-29 | 1976-11-29 | Exclusive logical sum circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5368065A true JPS5368065A (en) | 1978-06-17 |
JPS5739092B2 JPS5739092B2 (en) | 1982-08-19 |
Family
ID=15333745
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14322376A Granted JPS5368065A (en) | 1976-11-29 | 1976-11-29 | Exclusive logical sum circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5368065A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS56129428A (en) * | 1980-03-14 | 1981-10-09 | Fujitsu Ltd | Logic circuit |
US4626711A (en) * | 1984-05-11 | 1986-12-02 | National Semiconductor Corporation | Exclusive or gate circuit |
-
1976
- 1976-11-29 JP JP14322376A patent/JPS5368065A/en active Granted
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS56129428A (en) * | 1980-03-14 | 1981-10-09 | Fujitsu Ltd | Logic circuit |
US4626711A (en) * | 1984-05-11 | 1986-12-02 | National Semiconductor Corporation | Exclusive or gate circuit |
Also Published As
Publication number | Publication date |
---|---|
JPS5739092B2 (en) | 1982-08-19 |
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