JPS6425626A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS6425626A
JPS6425626A JP62181060A JP18106087A JPS6425626A JP S6425626 A JPS6425626 A JP S6425626A JP 62181060 A JP62181060 A JP 62181060A JP 18106087 A JP18106087 A JP 18106087A JP S6425626 A JPS6425626 A JP S6425626A
Authority
JP
Japan
Prior art keywords
circuit
clock signal
state buffer
parallel
circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62181060A
Other languages
Japanese (ja)
Other versions
JP2690083B2 (en
Inventor
Kozaburo Kurita
Shinichi Shinoda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP62181060A priority Critical patent/JP2690083B2/en
Priority to US07/184,782 priority patent/US5133064A/en
Priority to KR88004809A priority patent/KR950008019B1/en
Publication of JPS6425626A publication Critical patent/JPS6425626A/en
Priority to US07/487,125 priority patent/US5359727A/en
Priority to US07/872,174 priority patent/US5388249A/en
Priority to US08/278,245 priority patent/US5506982A/en
Priority to US08/279,887 priority patent/US5640547A/en
Priority to US08/460,601 priority patent/US5542083A/en
Priority to US08/788,831 priority patent/US5974560A/en
Application granted granted Critical
Publication of JP2690083B2 publication Critical patent/JP2690083B2/en
Priority to US10/002,444 priority patent/US6675311B2/en
Priority to US10/701,447 priority patent/US7111187B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE:To decrease the delay time of a clock signal and to eliminate the skew of the clock signal by using an output of a parallel circuit of a 3-state circuit incorporating a diagnostic circuit to all logic circuits so as to supply the clock signal. CONSTITUTION:A parallel circuit of a 3-state buffer circuit 5 receives a clock signal 12, the inside of the semiconductor substrate 1 is wired as a lattice and control clock signals 13 for logic blocks 61-68 dispersed in the entire inside of the substrate 1 are supplied to the entire circuit. In this case, all the parallel circuits of the tri-state buffer circuit 5 are brought into the operating state to drive surely the control clock signal 13 by the parallel circuit of the 3-state buffer circuit 5. Since the load driven by one of the 3-state buffer circuits 5 is small, the delay time by the parallel circuit of the 3-state buffer circuits 5 is small.
JP62181060A 1987-04-27 1987-07-22 Semiconductor integrated circuit device Expired - Fee Related JP2690083B2 (en)

Priority Applications (11)

Application Number Priority Date Filing Date Title
JP62181060A JP2690083B2 (en) 1987-07-22 1987-07-22 Semiconductor integrated circuit device
US07/184,782 US5133064A (en) 1987-04-27 1988-04-22 Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices
KR88004809A KR950008019B1 (en) 1987-04-27 1988-04-27 Information processing apparatus and system therefor
US07/487,125 US5359727A (en) 1987-04-27 1990-03-02 Clock generator using PLL and information processing system using the clock generator
US07/872,174 US5388249A (en) 1987-04-27 1992-04-22 Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices
US08/278,245 US5506982A (en) 1987-04-27 1994-07-21 Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices
US08/279,887 US5640547A (en) 1987-04-27 1994-07-26 Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices
US08/460,601 US5542083A (en) 1987-04-27 1995-06-02 Information processor and information processing system utilizing clock signal
US08/788,831 US5974560A (en) 1987-04-27 1997-01-27 Information processor and information processing system utilizing clock signal
US10/002,444 US6675311B2 (en) 1987-04-27 2001-12-06 Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices
US10/701,447 US7111187B2 (en) 1987-04-27 2003-11-06 Information processor and information processing system utilizing interface for synchronizing clock signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62181060A JP2690083B2 (en) 1987-07-22 1987-07-22 Semiconductor integrated circuit device

Publications (2)

Publication Number Publication Date
JPS6425626A true JPS6425626A (en) 1989-01-27
JP2690083B2 JP2690083B2 (en) 1997-12-10

Family

ID=16094082

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62181060A Expired - Fee Related JP2690083B2 (en) 1987-04-27 1987-07-22 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JP2690083B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5013942A (en) * 1988-08-19 1991-05-07 Kabushiki Kaisha Toshiba Clock supply circuit having adjustment capacitance
JPH04113673A (en) * 1990-09-03 1992-04-15 Mitsubishi Electric Corp Gate array
US6425046B1 (en) 1991-11-05 2002-07-23 Monolithic System Technology, Inc. Method for using a latched sense amplifier in a memory module as a high-speed cache memory

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57136235A (en) * 1981-02-16 1982-08-23 Nec Corp Driving semiconductor integrated circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57136235A (en) * 1981-02-16 1982-08-23 Nec Corp Driving semiconductor integrated circuit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5013942A (en) * 1988-08-19 1991-05-07 Kabushiki Kaisha Toshiba Clock supply circuit having adjustment capacitance
JPH04113673A (en) * 1990-09-03 1992-04-15 Mitsubishi Electric Corp Gate array
US6425046B1 (en) 1991-11-05 2002-07-23 Monolithic System Technology, Inc. Method for using a latched sense amplifier in a memory module as a high-speed cache memory
US6483755B2 (en) 1991-11-05 2002-11-19 Monolithic System Technology, Inc. Memory modules with high speed latched sense amplifiers

Also Published As

Publication number Publication date
JP2690083B2 (en) 1997-12-10

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees