JPH04113673A - Gate array - Google Patents

Abstract

PURPOSE:To reduce influence of noise in a sub clock driver, a main clock driver by disposing predetermined number of clock drivers on an input/output buffer cell region, and disposing a plurality of sub clock drivers corresponding to the drivers at both ends of a logic cell row composed as a logic gate of basic cell rows. CONSTITUTION:Sub clock drivers 7, 8 disposed at both ends of a logic cell row 4 are connected at input sides to annular signal wirings 6, and at output terminals all to the same signal wiring 9. That is, the wirings 9 have parallel wirings 9 parallel to the logic cell row for connecting the output terminals of the sub clock drivers at both ends of the logic cell row, first vertical wirings 9b arranged in a direction perpendicular to the logic cell row and connected with the output terminals of all the sub clock drivers 7 of one end side of the cell row, and second vertical wirings 9c arranged in parallel with the wirings 9b and connected with the output terminals of all the sub clock drivers of the other end side of the cell row.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a gate array, and particularly to a layout of a clock distribution method that suppresses clock skew in a system.

[Conventional technology]

Generally, the number of flip-flops hanging from a clock line increases as the gate size increases, and the need for high-speed operation has made it necessary to suppress clock skew.

Conventionally, there has been a tree structure system in which several sub-clock drivers are connected to one clock driver, and a flip-flop is connected to the sub-clock driver.
Due to differences in load size, etc., the speed of each sub-clock driver was not constant, resulting in large skews. Furthermore, attempts to control the size of the load and keep the speed constant are difficult in gate arrays, which can be developed in a short period of time using automatic layout tools.

FIG. 4 is a plan view of a chip showing a conventional gate array clock distribution system, and shows an example of the above tree structure. In the figure, 1 is a gate array chip, 4 is a basic cell or a regularly arranged cell row, and this basic cell consists of at least one p-type transistor and at least one n-type transistor. 3 is a wiring channel region of the gate array chip 1, 2 is an input/output buffer cell region around the gate array chip where input/output buffer cells are arranged, and 15 is a clock input area arranged in the buffer cell region 2. Buffer (clock driver)
, 10 are some basic cell clock input buffers 1
a first clock signal line connected to the output of 5, 17
The sub-clock driver 19 connected to the clock signal line 16 is a second clock signal line that connects the sub-clock driver 17 and the flip-flop 10.

Next, the operation will be explained.

The clock signal passes through the clock input buffer 15 and the first clock signal line 16 to each sub-block driver 1.
distributed to 7.

The distributed clock signal is then transmitted to each flip-flop 10 hanging from each sub-clock driver 17. In this case, there are variations in the number of flip-flops IO attached to each sub-clock driver 17 (load capacitance) and the wiring length (resistance) from the sub-clock driver 17 to each flip-flop IO, and the larger the number, the greater the skew. Become.

FIG. 5 is a plan view of a gate array chip showing a conventional method of collectively applying a clock signal to flip-flops in a gate area inside the chip.

In the figure, the same symbols as in Figure 4 indicate the same things, and 2
Reference numeral 5 denotes a clock driver disposed in the input/output buffer cell area 2;
0 are directly connected to the clock driver 25 via clock signal lines 26.

In the gate array having such a configuration, the clock signal transmitted to the clock driver 25 is distributed all at once to the flip-flop 10 and the like via the clock signal line 26. For this reason, the clock driver 25 is designed here with a transistor size that has sufficient ability to drive a large number of flip-flop groups. In other words, unlike the tree structure, it is driven all at once, so there is no need to worry about adjusting the load capacitance or wiring length, but since the load capacitance attached to the clock driver 15 is very large, the drive capacity is increased. Therefore, clock driver 1
5's switching noise and the area it occupies becomes a problem. Also, the F/F closest to the clock driver 15
The skew between F/F and the farthest F/F is not as small as expected due to wiring resistance.

[Problems to be Solved by the Invention] Since the conventional clock distribution system in the gate array is configured as described above, it has the following problems.

First, in the case of the tree structure shown in FIG. 4, the sub-clock drivers are distributed within the logic cell column, so
The drive power line for the flip-flop and the sub-clock driver is common, so there is a problem in that noise generated in the sub-clock driver enters the flip-flop, that is, the logic cell side. In addition, it is necessary to adjust the wiring length and fan-out (FO) number, that is, the number of flip-flops attached to the sub-clock driver, at the time of layout, which is extremely difficult with automatic layout tools.

Furthermore, in the case of the -finger drive type system, since a driver with a large transistor size is used, there are problems in that the influence of noise on the logic cell side is large and the area occupied in the input/output buffer cell is large.

The present invention was made to solve the above-mentioned problems, and an object of the present invention is to obtain a gate array that can reduce the influence of noise in the sub-clock driver and the main clock driver.

In addition to reducing the noise described above, the present invention eliminates the influence of the wiring length from the sub-clock driver to the flip-flop on the skew, and provides a gate array that can realize clock distribution with small clock skew even on automatic placement and routing CAD. The purpose is to

[Means to solve the problem]

In the gate array according to the present invention, a clock driver is divided into a main clock driver and a plurality of sub-clock drivers, and each sub-clock driver is arranged at both ends of each gate cell column.

Further, in the gate array, the wiring on the output side of the sub-clock driver is connected to the output terminals of all the sub-clock drivers, and the sub-signal wiring is directly connected to the output terminals of the sub-clock drivers at both ends of the gate cell column. It is something.

Further, in the present invention, in the gate array, the wiring on the output side of the clock driver is a ring-shaped signal wiring to which inputs of a plurality of sub-clock drivers corresponding to the clock driver are connected.

[Effect]

In this invention, since the sub-clock drivers are arranged at both ends of each gate cell column, the power supply line of the sub-clock driver and the logic cell.

In other words, it is possible to separate the power supply line of the flip-flop, thereby preventing noise generated by the sub-clock driver from entering the logic cell side.

In addition, since the clock driver is divided into the main clock driver and multiple sub-clock drivers, the drive capacity of the main clock driver can be reduced, and as a result, the noise generated and the area occupied by the input/output buffer area can be reduced. .

In addition, since the output terminals of the sub-clock driver on both sides of the logic cell column are directly connected to each logic cell column, the influence of the wiring length skew from the sub-clock driver to the flip-flop is eliminated, and the clock skew can be adjusted even on automatic placement and routing CAD. A small clock distribution can be realized.

Furthermore, since the wiring connecting the clock driver and the sub-clock driver is a ring-shaped wiring, the skew in each sub-clock driver can be reduced.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a plan view for explaining a gate array according to an embodiment of the present invention. In the figure, the same reference numerals as in FIG. The output side of the main clock driver is a ring-shaped wiring 6. Further, 7 and 8 are sub-clock drivers arranged at both ends of the logic cell row (hereinafter also referred to as gate cell row) 4 configured as a logic gate among the basic cell rows, and the input side thereof is connected to the above-mentioned ring-shaped signal wiring 6. It is connected. Further, the output terminals of the sub-clock driver buffers 8 are all connected to the same signal wiring (sub-signal wiring) 9.

In other words, the signal wiring 9 is arranged for each logic cell column,
Parallel wiring 9a parallel to the logic cell column connecting the output terminals of the sub-clock drivers at both ends of the logic cell column, and all sub-clocks at one end of each logic cell column arranged in a direction perpendicular to the logic cell column. A first vertical wiring 9b to which the output terminal of the driver buffer is connected, and a second vertical wiring 9b arranged parallel to the wiring 9b to which the output terminals of all the sub-clock drivers on the other end of the logic cell column are connected. It consists of a wiring 9c. A flip-flop 1o operated by a system clock is connected to the parallel wiring 9a.

Next, the operation will be explained.

A system clock signal enters a clock driver 5 and is distributed via a clock signal line 6 to sub-drivers 7.8 arranged at both ends of each gate cell column 4. The clock signal transmitted to the sub-driver is signal wire 9
is finally distributed to each F/F l O through.

In this way, in this embodiment, the sub clock driver buffer, 8
are placed at both ends of each gate cell column, it is possible to separate the power line of sub-clock driver line 8 from the power line of the logic cell, that is, the flip-flop, which reduces the noise generated by the sub-clock driver. This can prevent it from entering the logic cell side.

In addition, since the clock driver is divided into the main clock driver 5 and multiple sub-clock driver buffers 8, the drive capacity of the main clock driver can be reduced, resulting in noise and input/output buffer area 2. The area occupied by the device can be reduced. Therefore, a large number of clock drivers can be arranged in the input/output buffer area 2.

Also sub-clock driver buffers on both sides of the logic cell row.

Since the output terminal of 8 is directly connected to each logic cell column, the effect on the skew of the wiring length from sub-clock driver buffer 8 to flip-flop 10 is eliminated, and clock distribution with small clock skew can be achieved even on automatic placement and routing CAD. can be realized.

Furthermore, clock driver 5 and sub clock driver buffer,
Since the wiring connecting 8 is made into an annular wiring, the skew in each sub-clock driver buffer 8 can be reduced.

In the above embodiment, as shown in FIG. 1, the sub-signal wirings include the parallel wiring 9a and the first . Although a device having second vertical wirings 9b and 9c is used, in addition to these wirings, a device having a third vertical wiring connecting parallel wirings 9a of each logic cell column may be used. The skew can be further reduced by Also this third
There may be a plurality of vertical wirings, in which case the first... It is preferable to arrange them evenly between the second wirings.

Further, in the above embodiment, a case is shown in which F/Fs are arranged in all the gate cell rows, but this may also be the case where there is no F/F in the gate cell row 4' as shown in FIG. in this case,
If parallel wiring is provided even in a gate cell example without a flip-flop, there is no need to make any changes to the automatic placement and wiring CAD program, which is preferable in terms of handling.

Furthermore, as shown in FIG. 3, it goes without saying that parallel wiring may not be arranged in the logic cell column 4' without flip-flops.

〔Effect of the invention〕

As described above, according to the present invention, since the sub-clock drivers are arranged at both ends of each gate cell column, the power line of the sub-clock driver and the power line of the logic cell can be separated, and the sub-clock driver The influence of noise on logic cells can be reduced. Furthermore, since the clock driver is divided into a main clock driver and a plurality of sub-clock drivers, the main clock driver can be made smaller and its noise and occupied area can be reduced.

In addition, since the output terminals of the sub-clock drivers on both sides of the logic cell column are connected for each logic cell column, the effect of the wiring length from the sub-clock driver to the flip-flop on the skew is eliminated, and clock skew can be easily adjusted on automatic placement and routing CAD. This has the effect of realizing small clock distribution.

Furthermore, since the wiring connecting the clock driver and the sub-clock driver is made into a ring-shaped wiring, there is an effect that the skew in each sub-clock driver can be reduced.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a clock distribution system according to an embodiment of the present invention, FIGS. 2 and 3 are diagrams showing a clock distribution system according to another embodiment of the invention, and FIG. 4 is a diagram showing a clock distribution system according to another embodiment of the invention. FIG. 5 is a diagram showing a clock distribution method using a conventional batch drive. In the figure, 1 is a gate array chip, 2 is an input/output buffer area, 4 is a basic cell, 5 is a main clock driver, 6 is a clock signal line, 9 is a sub-clock signal line,
9a is the parallel wiring, 9b and 9C are the first. second vertical wiring,
10 is a flip-flop. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (4)

[Claims] (1) A basic cell area in which basic cells consisting of first conductivity type transistors and second conductivity type transistors are regularly arranged inside the chip, and input/output buffer cells that interface with the outside of the LSI around the basic cell area are arranged. In the gate array having an input/output buffer cell area, a predetermined number of clock drivers are placed in the input/output buffer cell area, and a plurality of sub-clock drivers corresponding to the clock driver are placed in the logic area of the basic cell array. A gate array characterized in that it is arranged at both ends of a logic cell column configured as a gate. (2) The gate array according to claim 1, wherein the wiring on the output side of the sub-clock driver is a common sub-signal wiring to which the output terminals of all the sub-clock drivers are connected. (3) In the gate array according to claim 2, the sub-signal wiring is arranged for each logic cell column, and is parallel to the logic cell columns connecting the output terminals of the sub-clock drivers at both ends of the logic cell column. a first vertical wiring arranged in a direction perpendicular to the logic cell column and connected to the output terminals of all sub-clock drivers at one end of each logic cell column, and parallel to the first vertical wiring; 1. A gate array comprising: a second vertical wiring line arranged at the second end of the logic cell column and connected to the output terminals of all the sub-clock drivers on the other end side of the logic cell column. (4) The gate array according to claim 1, wherein the wiring on the output side of the clock driver is a ring-shaped signal wiring to which inputs of a plurality of sub-clock drivers corresponding to the clock driver are connected. array.