JPH03238844A - Gate array - Google Patents

Abstract

PURPOSE:To enable clock skew to be suppressed, prevent the number of I/O pins from being reduced, and enable a power supply pin and I/O pin to be arranged flexibly by using an I/O buffer cell region as a power supply or a grounding pin and by using a transistor within that region as a transistor for clock driver. CONSTITUTION:A transistor of an I/O buffer cell 4 is used as a clock driver 11 and that region is used as a power supply pin or a grounding pin instead of an I/O pin. Namely, a clock driver 11 is placed under a power supply wire 13/a grounding wire 14 of a power supply pin or a grounding pin region 9, all are formed by a first-layer wiring, and a clock signal is supplied to a flip flop at a region within the chip, thus enabling influence of noise due to operation of the clock driver 11 to be suppressed without reducing the number of I/O pins and a gate array where a clock skew is suppressed is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the arrangement of clock drivers in gate arrays that suppresses clock skew and suppresses the influence of noise.

[Conventional technology]

In general, the number of flip-flops hanging from a clock line increases as the gate size increases, and since they must operate at high speed, clock skew must be suppressed. Tree-structured systems have been available in the past, but due to differences in the size of the load, the speed of each driver was not constant, resulting in large skews. In addition, attempts to control the size of the load and keep the speed constant use automatic layout tools.
This was difficult for gate arrays, which had to be developed in a short period of time. FIG. 6 is a plan view of a chip showing a conventional method of distributing clocks in a gate array and suppressing skew. In the figure, (29) is a gate array chip, (30
) is a cell column in which basic cells are arranged regularly, (3
1) is the wiring channel area, (32) is the input/output buffer cell, (33> is the pad, (34) is the beam lock input pad, (35) is the clock input buffer, (36) is the clock signal line, (37) is the subclock driver
(38) is a clock signal line that is manually input to the flip-flop, (39) is a power supply bin area, and (40) is a power supply pad.

A clock signal is applied from a pad (34), passes through a clock input buffer (35) and a signal line (36), and is distributed to each sub-clock driver (37).The distributed clock signal is then applied to each sub-driver. It is transmitted to the hanging flip-flops.In this case, the number of flip-flops attached to each sub-driver (load capacity)
are different, and the larger the difference, the larger the skew.

FIG. 7 is a plan view of a gate array chip showing a conventional method of collectively applying a clock signal to flip-flops in a gate area inside the chip.

In the figure, (41) is a clock driver (42> is an output signal line of the clock driver).

Moreover, FIG. 8 shows a partially enlarged plan view of FIG. 7. Since the load capacitance attached to the clock driver is very large, it is configured using transistors in the input/output buffer cell area (32). In the figure, (43) is the output buffer power wiring line, (44) is the output buffer ground wiring line, (45) is the input buffer/pre-buffer power wiring line (46) is the manual buffer/pre-buffer ground wiring line. line, (47) is a pMOS transistor for the output buffer, (48) is an nMOS transistor for the output buffer,
(49) is a PMOS transistor for input buffer/prebuffer, (50) is n for manual buffer/prebuffer
It is a MOS transistor.

The clock driver (41) is the human output buffer cell (3
2) transistors (47) (48) (49) (50
), and the output signal line (42) is connected to an internal flip-flop.In this method, the output buffer cell (32) is not used as a normal input/output buffer, so the number of I10 pins is reduced. become.

Furthermore, if the clock driver (41) is not placed near the power supply bin/ground bin, the influence of noise must be considered.

FIG. 9 is an enlarged plan view of part 4 showing the case of a flexible power supply that uses the input/output buffer cell area as a power supply bin/ground bin, but the number of I10 pins is reduced as in the case of FIG. 8.

[Problem to be solved by the invention]

The clock driver in a conventional gate array is configured as described above, so when it is divided into sub-drivers, the delay time of each sub-driver is controlled to be constant,
It is difficult to suppress the skew as long as automatic layout CAD is used, and in the case of a one-type clock driver type that is collectively driven, it is necessary to secure a transistor area for the clock driver in the input/output buffer area, and the number of I10 pins increases. If the clock driver area is reduced or the clock driver dedicated area is fixed, there are problems such as the inability to flexibly accommodate the bin arrangement for various users.

This invention was made in order to solve the above-mentioned problems, and provides a gate array that suppresses clock skew, does not reduce the number of I10 bins, and can flexibly accommodate the arrangement of power supply bins and input/output bins. With the goal.

[Means for Solving the Problem 1] The gate array according to the present invention uses the human output buffer cell area as a power supply or grounding bin, and uses the transistors in the area as clock driver transistors.

[Effect]

The clock driver in this invention uses the transistors of the output buffer cells, and that area is not used as an input/output bin, but as a power supply or ground bin. In other words, a clock driver is placed under the power wiring/ground wiring in the power supply bin or ground bin area, is formed entirely by the first layer wiring, and the clock signal is supplied to the flip-flop in the chip internal area.

(Example) Hereinafter, an example of the present invention will be explained with reference to the drawings.
In the figure, (1) is the gate array chip, (2) is the basic cell column, (3) is the wiring channel region, (4) is the input/output buffer 7 cell, and (5) is the pad for the human output buffer cell (4). , (6) is the clock manual pad, (7) is the clock manual buffer, (8) is the signal line from the clock manual buffer (7) to the clock driver, (9) is the power supply bin area, and (10) is the power supply bat. , (!l) is the clock driver (12) is the clock driver (11)
This is a clock signal line that connects the output of the circuit to the clock terminal of each flip-flop in the internal area.

A clock signal is applied to a pad (6), passes through a clock manual buffer (7), and is transmitted through a signal line (8) to a clock driver (11). Clock driver (1
1) is placed in the power pin area (9). The clock signal is then transmitted to each flip-flop via a clock driver (11) and a clock signal line (12).

Here, the transistor in the power pin region (9) is the same as the transistor in the input/output buffer cell (4).

FIG. 2 shows a partially enlarged plan view of the input/output buffer cell (4) region of FIG. 1. In the figure, (13) is the power wiring line for the output buffer, (14) is the ground wiring line for the output buffer, (15) is the power wiring line for the manual buffer and pre-buffer, and (16) is the ground wiring for the input buffer and pre-buffer. Line, (17) is PMOS transistor for output buffer, (18) is nMOS transistor for output buffer, (19) is pM for input buffer and pre-buffer.
The OS transistor (20) is a manual buffer and a pre-buffer nMOS transistor, and (21) is a grounding pad.

Input/output buffer cells (4) are arranged at equal intervals,
This part will be made into a power pin area (9) and a ground bin area.

Then, as shown in FIG. 3, a clock driver (11) is formed by the first layer of wiring. Figure 3 shows wiring for the transistor under the power pin area (9) in Figure 2.
This is a plan view in which an output buffer 7 is configured by wiring a clock driver and transistors under the input/output buffer cell area (4) in FIG. 2.

Note that although the above embodiment shows the case where the clock driver is constructed using the transistors under the power supply pin area (9), the transistors under the ground bin area may also be used.

In addition, although FIG. 3 shows the case where the pre-driver of the clock driver (11) is composed of input buffer/pre-buffer transistors (19) and (20), as shown in FIG. ) (1B
).

Further, although the above embodiment shows the case where there is only one clock driver, there may be two or more clock drivers as shown in FIG. Also, the clock signal that enters the clock driver's input need not come directly from the clock manual buffer.

In FIG. 5, (22) is a clock input pad, (
23) is a clock human buffer (24) is a signal line,
(25) is the power pin area, (26) is the power pad, (2
7) is a clock driver (28) is a clock signal line.

[Effects of the Invention] As described above, according to the present invention, input/output buffer cells are arranged at regular intervals, a part of them is assigned to the power supply bin or the ground bin, and the transistors under that area are used as clock drivers. Therefore, it is possible to suppress the influence of noise caused by the operation of the clock driver without reducing the number of I10 bins, and to realize a gate array with suppressed clock skew.

[Brief explanation of drawings]

FIG. 1 is an overall plan view of a gate array chip in which a clock driver according to an embodiment of the present invention is laid out, and FIG. 2 is a transistor arrangement in the human output buffer cell area before the wiring constituting the clock driver in FIG. 1 is installed. 3 is a partially enlarged plan view showing the clock driver shown in FIG. 2, and FIG. 4 is a partially enlarged plan view showing the clock driver according to another embodiment of the present invention. , FIG. 5 is an overall plan view of a gate array chip according to another embodiment of the present invention, FIG. 6 is an overall plan view of a gate array chip using a conventional clock distribution method, and FIG.
The figure is an overall plan view of a conventional gate array chip using a clock batch drive method, FIG. 8 is a partially enlarged plan view of the input/output buffer area of FIG. 7, and FIG. 9 is another conventional example of FIG. 8. FIG. 3 is a partially enlarged plan view of a human output buffer area in the case of a flexible power supply system. In the figure, (1) is a gate array chip, (2) is a basic cell column, (3) is a wiring channel region, (4) is an input buffer cell, (5) is a pad, (6) is a clock input pad, (7) is a clock manual buffer, (8) is a signal line, (9) (25) is a power pin area, (10) (26)
are power supply pads, (11) and (27) are clock drivers, (12) are clock signal lines, (13) and (15) are power supply wiring lines, (14) and (16) are ground wiring lines, and (1
7) (19) is a PMOS transistor, (18) (20
) is nMOS transistor, (21) ground pad, (2
4) is a signal line, and (28) is a clock signal line. In addition, the same symbols in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] A plurality of basic cells consisting of at least one or more first conductivity type transistors and at least one or more second conductivity type transistors are regularly arranged inside the chip, and interfaced with the outside of the LSI around the basic cell area. In a gate array comprising an area in which input/output buffer cells are arranged, each having a pad for each output buffer cell, some of the input/output buffer cells provided in advance around the chip are connected to a power source or a ground. A gate array characterized in that the transistors in the input/output buffer cell area are used as clock driver transistors.