JPH0764667A - Semiconductor device and clock signal supplying method - Google Patents

Abstract

PURPOSE:To prevent the malfunction and the heat generation of a chip even in the case that the size of a clock driver is enlarged in order to suppress the phase difference of a clock signal below a prescribed value. CONSTITUTION:The clock driver 12 is not installed on a microprocessor 13, but it is installed at another place on a base board 10. Then, the clock signal is supplied to the microprocessor 13 from the clock driver 12 through a solder bump group 14, wiring 15 and the solder bump group 16. At a microprocessor 13 side operated synchronously with the clock signal, the clock signal supplied from the clock driver 12 is transmitted directly to a latch, etc., by using low- skew wiring such as equal-length wiring, etc.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device and method for distributing a clock signal to each active circuit in a semiconductor device.

[0002]

2. Description of the Related Art In a semiconductor device, a method as shown in FIG. 9 has been conventionally used as a method for distributing a clock signal to each part on a chip. That is, the clock signal applied to the bonding pad 1 from outside the chip passes through the protection circuit 2 for preventing the semiconductor integrated circuit from being destroyed by static electricity, and then applied to the waveform shaping circuit 3.
The waveform shaping circuit 3 removes noise on the input signal and converts it into a voltage level inside the semiconductor integrated circuit. The output of the waveform shaping circuit 3 is added to the frequency divider 4 and converted into an operation clock of the semiconductor integrated circuit. Then, this operation clock is transmitted to each latch 8 in the semiconductor integrated circuit through the multi-stage clock driver 5. At this time, in order to make the phase difference between the two end clocks 6 and 7 equal to or less than the specified value, the fanout and wiring length of each clock driver can be made uniform, and the size of the clock driver can be optimized. It is being appreciated.

Details of such a conventional example are described in the following documents. 'A 200MHz 64-b Dual Issue
CMOS Microprocessor 'Daniel W.
Dubberpuhlet. al. IEEE Journal of Solid-sta
te Circuits, vol.27, Novembe
r 1992, pp.1555-1567.

[0004]

However, the above-mentioned conventional techniques have the following problems. That is, since there is inevitably some variation in fan-out and wiring length, it is necessary to increase the size of the clock driver in order to keep the phase difference of the clock signals below the specified value. Therefore, the following three problems occur.

First, the noise generated by the clock driver becomes large and the circuits in other parts of the semiconductor integrated circuit malfunction. Second, since the power consumed by the clock driver is as large as 15 to 20% of the power consumed by the entire chip, the amount of heat generated by the semiconductor integrated circuit increases, and the power consumption of one chip has an upper limit. Less. Thirdly, since the driver occupies a large area on the semiconductor integrated circuit, the number of functions that can be mounted on one chip also decreases.

An object of the present invention is to provide a semiconductor device and a clock signal capable of suppressing the occurrence of malfunction and heat generation of a chip even when the size of the clock driver is increased in order to keep the phase difference of the clock signal below a specified value. It is to provide a supply method.

[0007]

In order to achieve the above object, the present invention comprises a clock driver for controlling a clock signal and a plurality of active circuits which operate in synchronization with the clock signal from the clock driver. In a semiconductor device provided with the clock driver, the clock driver is arranged avoiding a chip provided with the active circuit, and a clock signal from the clock driver is supplied to the active circuit from outside the chip while the supplied clock is supplied. Means is provided for keeping the phase difference of the signals between the respective active circuits below a predetermined value.

According to the present invention, in a semiconductor device including a clock driver for controlling a clock signal and a plurality of active circuits which operate in synchronization with the clock signal from the clock driver, the active circuit is provided. While arranging the clock driver while avoiding on the chip, a plurality of input points for inputting a clock signal from the clock driver to the chip and a delay time of the clock signal input to each of the input points are set. A plurality of wirings, which are made substantially equal to each other between the active circuits and are transmitted to the active circuits, are provided on the chip.

Further, according to the present invention, in a semiconductor device including a clock driver for controlling a clock signal and a plurality of active circuits operating in synchronization with the clock signal from the clock driver, the active circuit is provided. While arranging the clock driver while avoiding on the chip, a plurality of input points for inputting a clock signal from the clock driver to the chip and two or more of the active circuits for each input point are provided. Two or more wirings, which are connected to each other and transmit the delay time of the clock signal input to each of the input points to the active circuits so that the delay times of the connected active circuits are substantially equal to each other, are provided on the chip. Is.

Further, according to the present invention, a clock driver for controlling a clock signal is arranged avoiding on a chip provided with a plurality of active circuits which operate in synchronization with the clock signal, and the active circuit is provided from outside the chip. In addition to supplying a clock signal to the circuit, the clock signal supplied to the chip is transmitted to each active circuit such that the phase difference between the active circuits becomes a predetermined value or less.

[0011]

According to the above structure, since the clock driver is not provided on the chip, noise generated on the chip can be reduced.
Further, since the clock driver is not provided on the chip, the power consumed by the chip is reduced, and the heat generation of the chip can be suppressed. Further, since there is no clock driver on the chip, the size of the chip can be reduced, and the portion occupied by the conventional clock driver can be used as an element for improving the function of the semiconductor integrated circuit.

Further, the clock signal input from the clock driver to the chip is supplied to each active circuit with the phase difference between the active circuits being a predetermined value or less, and the skew between the active circuits can be reduced.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 shows an example of a microprocessor application system to which the present invention is applied. In this system, a clock generator 11, a clock driver 12, and a microprocessor 13 are provided on a ceramic substrate 10 with CCB (Co
It is mounted using ntrolled Collapse Bonding) technology. The clock driver 12 is not included in the microprocessor 13, and a clock signal is supplied from the clock driver 12 to the microprocessor 13 via the solder bump group 14, the wiring 15 in the ceramic substrate, and the solder bump group 16. The microprocessor 13 directly distributes the supplied clock signal to each latch to operate it. The length of wiring between chips is about 3 cm.
From the clock driver 12 to the clock generator 11
A clock having a duty ratio of 1: 1 and a frequency of 200 MHz generated in step 3 is supplied.

Inside the microprocessor 13, FIG.
The clock is distributed like this. A clock is supplied from outside the chip through the solder bump group 16 of about 40 pieces. This clock first passes through a protection circuit 17 including a junction capacitance using a PN junction of the source and drain of a MOS transistor and a diode clamp circuit.
After that, it is distributed to each latch using the wiring 18.

The wiring 18 is a fractal pattern in which H-shaped branching is repeated, and the wiring lengths from the solder bump group 16 to the latches 20, 21, 22, ... Are almost equal. In addition, in order to improve electromigration resistance, the width of the wiring 18 is made thicker near the solder bump group 16 and thinner at the farther side. Skew occurs due to a slight variation in the wiring length, but the drive capability of the clock driver 12 provided outside the chip is set so that the skew becomes a predetermined value or less. Further, although the latch is directly connected to the end of the wiring 18, since the protection circuit 17 and the long wiring 18 are provided, even if a sharp pulse is applied to the solder bump group 17, the latch 20, 21, 22, 22 is provided.
I'm foolish at ... For this reason, electrostatic breakdown resistance is sufficient.

The latches include latches 20 and 21 with clock enable and latch 22 without clock enable.
There are two types. The latches 20 and 21 with a clock enable are latches that can operate not to take in data even when the clock is H (high level), and are mainly used to stop the pipeline of the microprocessor when register conflict occurs. . A total of about 10 ^{5 of} these latches are used in the microprocessor 13, and the total input capacitance thereof is about 10 nF.

Latches 20 and 2 with clock enable
The circuit of No. 1 is as shown in FIG. 3A, and a NAND gate is inserted in the clock input terminal of the latch 22 without the clock enable shown in FIG. 3B to mask the clock signal. . When the CKE terminal is at the L level, the latches 20 and 21 do not capture the value of the D terminal even when CK becomes H.

The inside of the clock driver 12 is as shown in FIG. The signal from the clock generator 20 enters through the solder bumps 19, is amplified by the four-stage inverter, and then goes out of the chip through the 40 solder bumps 14.

The waveform of the clock supplied from the clock driver 12 to the microprocessor 13 is as shown in FIG. FIG. 5A shows a voltage waveform. First, the voltage waveform is
Amplitude is 2.5V, both rise and fall times are 0.
5 ns, cycle time 5 ns, and duty ratio 1: 1. FIG. 5B shows a current waveform, which is approximated by a triangle. Since the additional capacitance is 10 nF, the peak current is 100 A, d
i / dt = 4 × 10 ¹¹ A / s. Therefore, the inductance of one solder bump is 0.04 nH, so 40
The number of solder bumps is 0.001 nH, and the voltage generated at both ends is 0.4 V, which is no problem.

FIG. 6 shows a modification of the microprocessor shown in FIG. The feature of this modification is that a solder bump group 16A is provided in addition to the solder bump group 16, and the solder bump group 16 is provided.
The clock input to A is supplied to the latches 20, 21, 22, ... Through the protection circuit 17A. Solder bump groups 16, 16A and each latch are 20, 2
.. are connected by a wiring 18A having the same length. By providing a large number of solder bump groups in this way, the input impedance can be reduced.

(Second Embodiment) FIG. 7 shows a second embodiment of the present invention. This embodiment is different from the above-described first embodiment in the inside of the microprocessor. Also in this embodiment, the clock is distributed from the solder bump group 24 to each part on the chip inside the microprocessor 23 through the protection circuit 25 and the equal-length wiring 26. A clock buffer 27 with a clock enable and a clock buffer 28 without a clock enable are provided at the end of the equal-length wiring 26 in total about 100.
0 is connected. Therefore, since the wiring lengths from the solder bump group 24 to the clock buffers 27 and 28 are almost equal, the skew between the clock buffers is small.

The clock buffer 27 has a maximum of 10
Latches 29 are connected, and the clock buffer 28 is also connected with a maximum of 10 latches 30. These latches are the latches without clock enable shown in FIG. When the number of latches is less than 10, a dummy load having the same size as the input capacitance of the latches is attached, and the delay from the clock buffer 27 or 28 to the latch 29 or 30 is almost the same everywhere.

In addition to the small skew between the clock buffers described above, the skew between the latches in the entire chip is small. The clock buffer 27 with a clock enable does not pass the clock signal input from the CK terminal when the CKE terminal is L as shown in FIG. 7B. Used to stop the pipeline of.

(Third Embodiment) FIG. 8 shows a third embodiment of the present invention. In this embodiment, a clock distribution system different from those of the above two embodiments is adopted. Inside the microprocessor 31, the latches are divided into two groups 32 and 33. Two solder bump groups 34 and 35 are provided corresponding to each latch group. Each of the latches 36 belonging to the latch group 32 is connected to the solder bump group 34 via a protection circuit 37 by an equal length wiring 38. Each latch 39 belonging to the latch group 33 is connected to the solder bump group 35 via a protection circuit 41 by an equal-length wiring 40. The equal length wirings 38 and 40 have the same wiring length. A low skew clock is supplied to the solder bump groups 34 and 35, and the skew between the latches in the entire chip is small. In the above structure, the solder bump group 34 and the solder bump group 35 may be connected.

(Fourth Embodiment) In the microprocessor of FIG. 8, the wiring lengths of the equal-length wiring 38 and the equal-length wiring 40 are made different between the latch groups 32 and 33. In this case, the clock in latch 36 and latch 39
Skew occurs between the input clock and the solder bump group 34 and the solder bump group 3 so as to compensate for the skew.
A phase difference is provided to the clocks supplied to the 5 and 5.

[0026]

As described above, according to the present invention,
The following effects can be expected. Since the clock driver is not provided on the chip, noise generation can be suppressed, and malfunction of the semiconductor integrated circuit can be prevented. Since the clock driver consumes no power on the chip, heat generation of the chip can be suppressed. Since the space occupied by the clock driver on the chip is eliminated, the size of the chip can be reduced and
Since there is no clock driver, an extra element for improving the function of the semiconductor integrated circuit can be incorporated. Since the driving capability of the clock driver can be increased regardless of power consumption and chip area, skew can be reduced.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of a semiconductor device of the present invention.

FIG. 2 is a configuration diagram of a microprocessor according to a first embodiment of the present invention.

FIG. 3 is a circuit configuration diagram of a latch in FIG.

FIG. 4 is a circuit configuration diagram of a clock driver.

FIG. 5 is a waveform diagram of current and voltage of a clock signal.

FIG. 6 is a diagram showing a modification of the microprocessor of FIG.

FIG. 7 is a configuration diagram of a microprocessor and a circuit configuration diagram of a clock buffer according to a second embodiment of the present invention.

FIG. 8 is a configuration diagram of a microprocessor according to a third embodiment of the present invention.

FIG. 9 is a block diagram of a conventional microprocessor.

[Explanation of symbols]

10 Ceramic Substrate 11 Clock Generator 12 Clock Driver 13, 13A, 23, 31 Microprocessor (Semiconductor Integrated Circuit) 14, 16, 16A, 19, 24, 34, 35 Solder Bump Group 15 Wiring 17, 17A, 25, 37, 41 Protection circuit 18, 18A, 26, 38, 40 Equal length wiring 20, 21, 22, 29, 30, 36, 39 Latch 27, 28 Clock buffer

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Takashi Hotta 7-1, 1-1 Omika-cho, Hitachi-shi, Ibaraki Hitachi Ltd. Hitachi Research Laboratory

Claims (9)

[Claims] 1. A semiconductor device comprising a clock driver for controlling a clock signal and a plurality of active circuits operating in synchronization with the clock signal from the clock driver, comprising: a chip provided with the active circuit; The clock driver is arranged avoiding it, and the clock signal from the clock driver is supplied from outside the chip to the active circuit, while the phase difference between the respective active circuits of the supplied clock signal is set to a predetermined value or less. A semiconductor device comprising means for performing. 2. The semiconductor device according to claim 1, wherein the means are provided between a plurality of active circuits and an input point on the chip to which a clock signal from the clock driver is input. A semiconductor device comprising wirings, wherein the delay time of a clock signal transmitted through the wirings is set to be substantially equal among the wirings. 3. A semiconductor device comprising a clock driver for controlling a clock signal, and a plurality of active circuits which operate in synchronization with the clock signal from the clock driver, wherein a chip provided with the active circuit is provided. While arranging the clock driver while avoiding it, a plurality of input points for inputting a clock signal from the clock driver to the chip and a delay time of the clock signal input to each of the input points are set to each active circuit. A semiconductor device, wherein a plurality of wirings which are made substantially equal to each other and are transmitted to each active circuit are provided on the chip. 4. The semiconductor device according to claim 3, wherein some of the plurality of input points are connected to one place on the chip. 5. A semiconductor device comprising a clock driver for controlling a clock signal and a plurality of active circuits that operate in synchronization with the clock signal from the clock driver, wherein a chip provided with the active circuit is provided. While arranging the clock driver while avoiding, a plurality of input points for inputting a clock signal from the clock driver to the chip, and two or more of the active circuits are connected to each of the input points. Two or more wirings for making the delay time of the clock signal input to each input point substantially equal between the connected active circuits and transmitting the same to the active circuits are provided on the chip. Semiconductor device. 6. The semiconductor device according to claim 5, wherein when the plurality of active circuits are divided into groups, the delay time of the clock signal between the groups is set to be substantially equal to each other. 7. The semiconductor device according to claim 5, wherein when the plurality of active circuits are divided into groups, the delay time of the clock signal between the groups is set differently. . 8. The semiconductor device according to claim 7, wherein the clock drivers output different clock signals so as to compensate for a difference in delay time of the clock signals. 9. A clock driver for controlling a clock signal is arranged avoiding on a chip provided with a plurality of active circuits that operate in synchronization with the clock signal, and the clock signal is supplied to the active circuit from outside the chip. And the clock signal supplied to the chip is transmitted to each active circuit such that the phase difference between the active circuits is equal to or less than a predetermined value.