JPS6424835U - - Google Patents

Info

Publication number
JPS6424835U
JPS6424835U JP12003387U JP12003387U JPS6424835U JP S6424835 U JPS6424835 U JP S6424835U JP 12003387 U JP12003387 U JP 12003387U JP 12003387 U JP12003387 U JP 12003387U JP S6424835 U JPS6424835 U JP S6424835U
Authority
JP
Japan
Prior art keywords
chip
wiring board
printed wiring
tab
hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12003387U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP12003387U priority Critical patent/JPS6424835U/ja
Publication of JPS6424835U publication Critical patent/JPS6424835U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Die Bonding (AREA)

Description

【図面の簡単な説明】
第１図は本考案のＴＡＢ化ＩＣチツプの実装状
態を示す断面図、第２図は本考案によるＩＣチツ
プの実装工程を示すブロツク図、第３図は従来の
ＴＡＢ化ＩＣチツプの実装状態を示す断面図、第
４図は従来のＩＣチツプの実装工程を示すブロツ
ク図、第５図はフイルムキヤリアの斜視図、第６
図は従来の傾いたＩＣチツプを示す断面図である
。 １……印刷配線基板、２……ＩＣチツプ、３…
…アウターリード、４……入出力導体部、５……
グランド導体部、６……メツキスルホール、７…
…接着剤、８……バンプ、９……フイルムキヤリ
ア。

Claims (1)

    【実用新案登録請求の範囲】
  1. ＴＡＢ化ＩＣチツプのグランド面を印刷配線基
    板のグランド導体面に対応させて装着し、ＩＣチ
    ツプのアウターリードを印刷配線基板の入出力導
    体面に対応させて、アウターリード・ボンデイン
    グして搭載する実装構造において、前記ＩＣチツ
    プを装着する印刷配線基板のグランド導体部にメ
    ツキスルホールを設け、スルホールに接着剤を流
    し込み、印刷配線基板にＩＣチツプを固着したこ
    とを特徴とするＴＡＢ化ＩＣの取付構造。
JP12003387U 1987-08-04 1987-08-04 Pending JPS6424835U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12003387U JPS6424835U (ja) 1987-08-04 1987-08-04

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12003387U JPS6424835U (ja) 1987-08-04 1987-08-04

Publications (1)

Publication Number Publication Date
JPS6424835U true JPS6424835U (ja) 1989-02-10

Family

ID=31365778

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12003387U Pending JPS6424835U (ja) 1987-08-04 1987-08-04

Country Status (1)

Country Link
JP (1) JPS6424835U (ja)

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