JPS642364A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS642364A
JPS642364A JP15834487A JP15834487A JPS642364A JP S642364 A JPS642364 A JP S642364A JP 15834487 A JP15834487 A JP 15834487A JP 15834487 A JP15834487 A JP 15834487A JP S642364 A JPS642364 A JP S642364A
Authority
JP
Japan
Prior art keywords
layer
source
gainas
gate
insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15834487A
Other languages
Japanese (ja)
Other versions
JPH012364A (en
Inventor
Mikio Kamata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP62-158344A priority Critical patent/JPH012364A/en
Priority claimed from JP62-158344A external-priority patent/JPH012364A/en
Publication of JPS642364A publication Critical patent/JPS642364A/en
Publication of JPH012364A publication Critical patent/JPH012364A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To lower source resistance, to remove the limitation of a short channel effect and to manufacture an SISFET and a MISFET having a short channel with high accuracy by forming source and drain regions by the same semiconductor layer and dividing the source and drain regions by a second conductor layer (an insulating layer) brought into contact with a first semiconductor layer.
CONSTITUTION: An undoped GaInAs layer 2 having a narrow band gap as a channel forming layer is epitaxial-grown onto a semi-insulating InP substrate 1 and an n+-GaInAs layer 13 in specified thickness as a source region and a drain region onto the layer 2. The layer 13 corresponding to a gate is etched selectively, and etched so as to be intruded into the layer 2. The source region 14 and the drain region 15 are shaped through said etching. An undoped AlInAs layer 3 as an insulating layer and an n+-GaInAs layer 4 having specified thickness as a gate electrode are grown through second epitaxial growth, and a photo-resist 18 is buried into a recessed section 17 corresponding to a gate section of the layer 4.
COPYRIGHT: (C)1989,JPO&Japio
JP62-158344A 1987-06-25 semiconductor equipment Pending JPH012364A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62-158344A JPH012364A (en) 1987-06-25 semiconductor equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62-158344A JPH012364A (en) 1987-06-25 semiconductor equipment

Publications (2)

Publication Number Publication Date
JPS642364A true JPS642364A (en) 1989-01-06
JPH012364A JPH012364A (en) 1989-01-06

Family

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