JPS642306B2 - - Google Patents
Info
- Publication number
- JPS642306B2 JPS642306B2 JP17149781A JP17149781A JPS642306B2 JP S642306 B2 JPS642306 B2 JP S642306B2 JP 17149781 A JP17149781 A JP 17149781A JP 17149781 A JP17149781 A JP 17149781A JP S642306 B2 JPS642306 B2 JP S642306B2
- Authority
- JP
- Japan
- Prior art keywords
- output
- shift register
- circuit
- signal
- bipolar
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000001514 detection method Methods 0.000 claims description 42
- 238000006467 substitution reaction Methods 0.000 claims description 19
- 238000006243 chemical reaction Methods 0.000 claims description 11
- 230000005540 biological transmission Effects 0.000 description 9
- 238000010586 diagram Methods 0.000 description 9
- 230000000694 effects Effects 0.000 description 3
- 238000000605 extraction Methods 0.000 description 3
- 230000000630 rising effect Effects 0.000 description 2
- 238000001208 nuclear magnetic resonance pulse sequence Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
- H04L25/40—Transmitting circuits; Receiving circuits
- H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
- H04L25/4917—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes
- H04L25/4923—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes using ternary codes
- H04L25/4925—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes using ternary codes using balanced bipolar ternary codes
Landscapes
- Physics & Mathematics (AREA)
- Spectroscopy & Molecular Physics (AREA)
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Dc Digital Transmission (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17149781A JPS5873263A (ja) | 1981-10-28 | 1981-10-28 | BnZS復号および誤り検出器 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17149781A JPS5873263A (ja) | 1981-10-28 | 1981-10-28 | BnZS復号および誤り検出器 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5873263A JPS5873263A (ja) | 1983-05-02 |
JPS642306B2 true JPS642306B2 (US06420036-20020716-C00037.png) | 1989-01-17 |
Family
ID=15924190
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17149781A Granted JPS5873263A (ja) | 1981-10-28 | 1981-10-28 | BnZS復号および誤り検出器 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5873263A (US06420036-20020716-C00037.png) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58115961A (ja) * | 1981-12-29 | 1983-07-09 | Fujitsu Ltd | 符号復号回路 |
JPH0616635B2 (ja) * | 1983-12-05 | 1994-03-02 | 富士通株式会社 | 誤りパルス検出回路 |
JPS6243920A (ja) * | 1985-08-21 | 1987-02-25 | Fujitsu Ltd | 復号回路 |
US10686469B2 (en) * | 2017-05-15 | 2020-06-16 | Qualcomm Incorporated | Payload size ambiguity and false alarm rate reduction for polar codes |
-
1981
- 1981-10-28 JP JP17149781A patent/JPS5873263A/ja active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS5873263A (ja) | 1983-05-02 |
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