JPS6421655A - Busy signal generating system for command control circuit - Google Patents

Busy signal generating system for command control circuit

Info

Publication number
JPS6421655A
JPS6421655A JP17949787A JP17949787A JPS6421655A JP S6421655 A JPS6421655 A JP S6421655A JP 17949787 A JP17949787 A JP 17949787A JP 17949787 A JP17949787 A JP 17949787A JP S6421655 A JPS6421655 A JP S6421655A
Authority
JP
Japan
Prior art keywords
chip
busy
command
busy signal
turned
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17949787A
Other languages
Japanese (ja)
Inventor
Tsutomu Akasaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP17949787A priority Critical patent/JPS6421655A/en
Publication of JPS6421655A publication Critical patent/JPS6421655A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To decrease the number of command control pins and to prevent a delay time from being large by suppressing the sending of a busy signal when commands received by respective chips are not for the charged function of the self-chip. CONSTITUTION:A command ending signal is sent to control chips 11-13 to take charge of a correspondent function and by executing the wired-OR of signals from the respective chips 11-13, the busy signal is sent to a requesting source. At the same time as the set of a command register, the respective chips certainly turn of the busy flug of the self-chip. However, command registers 31-33 are executed a decode and when it is not of the function of which the self-chip takes charge, the flag is turned off in the next cycle. Thus, only the busy flag of one chip is turned on, simultaneously, the busy flag of the other chip is turned off and the busy signal can be sent without contradiction. At such a time, the number of the chip pins in a command control circuit can be decreased.
JP17949787A 1987-07-17 1987-07-17 Busy signal generating system for command control circuit Pending JPS6421655A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17949787A JPS6421655A (en) 1987-07-17 1987-07-17 Busy signal generating system for command control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17949787A JPS6421655A (en) 1987-07-17 1987-07-17 Busy signal generating system for command control circuit

Publications (1)

Publication Number Publication Date
JPS6421655A true JPS6421655A (en) 1989-01-25

Family

ID=16066855

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17949787A Pending JPS6421655A (en) 1987-07-17 1987-07-17 Busy signal generating system for command control circuit

Country Status (1)

Country Link
JP (1) JPS6421655A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06180688A (en) * 1990-12-21 1994-06-28 Intel Corp Multiprocessor-interrupt controller system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06180688A (en) * 1990-12-21 1994-06-28 Intel Corp Multiprocessor-interrupt controller system

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