JPS6418773U - - Google Patents
Info
- Publication number
- JPS6418773U JPS6418773U JP11336687U JP11336687U JPS6418773U JP S6418773 U JPS6418773 U JP S6418773U JP 11336687 U JP11336687 U JP 11336687U JP 11336687 U JP11336687 U JP 11336687U JP S6418773 U JPS6418773 U JP S6418773U
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- printed wiring
- multilayer printed
- pad
- flat
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 239000011889 copper foil Substances 0.000 claims description 3
- 229910000679 solder Inorganic materials 0.000 description 1
Landscapes
- Insulated Metal Substrates For Printed Circuits (AREA)
Description
第１図ａ及びｂはそれぞれ本考案の第１の実施
例の平面図及びＡ―Ａ′線断面図、第２図は第１
図の実施例にフラツトＩＣを実装したときの多層
印刷配線板の平面図、第３図ａ及びｂはそれぞれ
本考案の第２の実施例の平面図及びＢ―Ｂ′線断
面図、第４図は第３図の実施例にフラツトＩＣを
実装したときの多層印刷配線板の平面図、第５図
は多層印刷配線板の内層銅箔の平面図、第６図ａ
及びｂはそれぞれ従来の多層印刷配線板の一例の
平面図及びＣ―Ｃ′線断面図、第７図はフラツト
ＩＣを実装したときの第６図の印刷配線板の平面
図である。
１，１ａ，１ｂ……多層印刷配線板、２……パ
ツド、３，３ａ，３ｂ……クリアランス、４，４
ａ，４ｂ……内層銅箔、５……フラツトＩＣ、６
……リード、７……はんだブリツジ、８……導通
ランド。
Figures 1a and b are a plan view and a sectional view taken along line A-A' of the first embodiment of the present invention, respectively, and Figure 2 is a cross-sectional view of the first embodiment of the present invention.
A plan view of a multilayer printed wiring board when a flat IC is mounted on the embodiment shown in the figure, FIGS. The figures are a plan view of a multilayer printed wiring board when a flat IC is mounted on the embodiment shown in Fig. 3, Fig. 5 is a plan view of the inner layer copper foil of the multilayer printed wiring board, and Fig. 6a.
and b are a plan view and a sectional view taken along the line CC' of an example of a conventional multilayer printed wiring board, respectively, and FIG. 7 is a plan view of the printed wiring board of FIG. 6 when a flat IC is mounted thereon. 1, 1a, 1b...Multilayer printed wiring board, 2...Pad, 3, 3a, 3b...Clearance, 4, 4
a, 4b...Inner layer copper foil, 5...Flat IC, 6
...Lead, 7...Solder bridge, 8...Continuity land.
Claims (1)
印刷配線板において、前記パツド位置に対応する
内層銅箔部に設ける矩形状のクリアランスを有す
ることを特徴とする多層印刷配線板。 A multilayer printed wiring board having a pad for mounting a flat IC component, the multilayer printed wiring board having a rectangular clearance provided in an inner layer copper foil portion corresponding to the pad position.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11336687U JPS6418773U (en) | 1987-07-23 | 1987-07-23 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11336687U JPS6418773U (en) | 1987-07-23 | 1987-07-23 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6418773U true JPS6418773U (en) | 1989-01-30 |
Family
ID=31353137
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11336687U Pending JPS6418773U (en) | 1987-07-23 | 1987-07-23 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6418773U (en) |
-
1987
- 1987-07-23 JP JP11336687U patent/JPS6418773U/ja active Pending
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