JPS6417292A - Static memory circuit - Google Patents

Abstract

PURPOSE:To execute read-out at a high speed, and to greatly take a margin against erroneous write at the time of a write operation, by making the word line amplitude at the time of write larger than that of the time of read-out and the time of holding. CONSTITUTION:At the time of a write operation, the collector potential of a transistor QW1 of a memory cell M11 is allowed to ascend, comparing with that of the time of a read-out operation. Accordingly, even if a high/low level difference of a read-out/write control signal WC1 is small, since the ON-side collector potential is allowed to ascend, a potential difference to a collector nodal point of an ON-side transistor of a memory cell M12 being in a holding state can be made larger at the time of write than at the time of read-out, there is no possibility of erroneous write, and the amplitude of a word line at the time of read-out can be made small. In such a way, the word line amplitude having a margin against erroneous write only at the time of write is secured, and the word line amplitude at the time of read-out and at the time of holding can be taken small, therefore, the time when the word line is driven can be executed at a high speed.