JPS648594A - Read only memory - Google Patents

Read only memory

Info

Publication number
JPS648594A
JPS648594A JP16424587A JP16424587A JPS648594A JP S648594 A JPS648594 A JP S648594A JP 16424587 A JP16424587 A JP 16424587A JP 16424587 A JP16424587 A JP 16424587A JP S648594 A JPS648594 A JP S648594A
Authority
JP
Japan
Prior art keywords
logical
depletion
ion implantation
polarity
power consumption
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16424587A
Other languages
Japanese (ja)
Inventor
Norihiko Ishizaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP16424587A priority Critical patent/JPS648594A/en
Publication of JPS648594A publication Critical patent/JPS648594A/en
Pending legal-status Critical Current

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  • Read Only Memory (AREA)

Abstract

PURPOSE:To reduce power consumption by switching the polarity of a readout output signal depending on whether depletion ion implantation is applied to a logical 0 of data or a written program or depletion ion implantation applied to logical 1. CONSTITUTION:When the number of logical 0s of data or program written in depletion ions is less than the number of logical 1s, the depletion ion implantation is applied to transistors 4-9 corresponding to the logical value in the ROM cell 2. When the number of logical 2s is less than the number of logical 0s, the depletion ion implantation is applied to the TRs 4-9 corresponding to the logical value 1. Then the polarity of the readout signal is inverted from the ROM 2 corresponding to the logical value and the depletion transistor and the enhancement N-channel transistor. Thus, a through-current is reduced regardless of the storage content to reduce the power consumption.
JP16424587A 1987-06-30 1987-06-30 Read only memory Pending JPS648594A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16424587A JPS648594A (en) 1987-06-30 1987-06-30 Read only memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16424587A JPS648594A (en) 1987-06-30 1987-06-30 Read only memory

Publications (1)

Publication Number Publication Date
JPS648594A true JPS648594A (en) 1989-01-12

Family

ID=15789435

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16424587A Pending JPS648594A (en) 1987-06-30 1987-06-30 Read only memory

Country Status (1)

Country Link
JP (1) JPS648594A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0271000A2 (en) * 1986-12-06 1988-06-15 BASF Aktiengesellschaft Flat material for optical laser recording
KR20000073002A (en) * 1999-05-04 2000-12-05 윤종용 ROM programmed with metal patterning to shorten TAT

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0271000A2 (en) * 1986-12-06 1988-06-15 BASF Aktiengesellschaft Flat material for optical laser recording
KR20000073002A (en) * 1999-05-04 2000-12-05 윤종용 ROM programmed with metal patterning to shorten TAT

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