JPS57111878A - Generating circuit of read reference level - Google Patents

Generating circuit of read reference level

Info

Publication number
JPS57111878A
JPS57111878A JP55188935A JP18893580A JPS57111878A JP S57111878 A JPS57111878 A JP S57111878A JP 55188935 A JP55188935 A JP 55188935A JP 18893580 A JP18893580 A JP 18893580A JP S57111878 A JPS57111878 A JP S57111878A
Authority
JP
Japan
Prior art keywords
level
input
word line
change
read reference
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55188935A
Other languages
Japanese (ja)
Inventor
Yasuhisa Sugao
Kazuhiro Toyoda
Katsuyuki Yamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55188935A priority Critical patent/JPS57111878A/en
Publication of JPS57111878A publication Critical patent/JPS57111878A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To set the read reference level in prior to the change of a word line and furthermore to realize the readout in a high speed, by detecting the time point when the word line shifts to selection from nonselection as an address change of a decoder input. CONSTITUTION:The tme point when a word line rises up to a selection level from a nonselection level is detected from an input change of a decoder DEC. The reference voltage level VR2 of a transistor T5 is compared with an input A1 of transistors T3 and T4 through a detecting circuit Z1 of address changing point to an input gate IG1. In such way, the read reference level is temporarily reduced in accordance with the input change and when the word line potential reses up to a selection level from a nonselection level.
JP55188935A 1980-12-26 1980-12-26 Generating circuit of read reference level Pending JPS57111878A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55188935A JPS57111878A (en) 1980-12-26 1980-12-26 Generating circuit of read reference level

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55188935A JPS57111878A (en) 1980-12-26 1980-12-26 Generating circuit of read reference level

Publications (1)

Publication Number Publication Date
JPS57111878A true JPS57111878A (en) 1982-07-12

Family

ID=16232466

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55188935A Pending JPS57111878A (en) 1980-12-26 1980-12-26 Generating circuit of read reference level

Country Status (1)

Country Link
JP (1) JPS57111878A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5438551A (en) * 1991-12-19 1995-08-01 Oki Electric Industry Co., Ltd. Semiconductor integrated circuit device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5438551A (en) * 1991-12-19 1995-08-01 Oki Electric Industry Co., Ltd. Semiconductor integrated circuit device

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