JPS6410826U - - Google Patents
Info
- Publication number
- JPS6410826U JPS6410826U JP10448587U JP10448587U JPS6410826U JP S6410826 U JPS6410826 U JP S6410826U JP 10448587 U JP10448587 U JP 10448587U JP 10448587 U JP10448587 U JP 10448587U JP S6410826 U JPS6410826 U JP S6410826U
- Authority
- JP
- Japan
- Prior art keywords
- processing device
- interface
- data
- serial
- parallel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Information Transfer Systems (AREA)
Description
第１図は本考案の実施例の構成図、第２図は本
考案の実施例のタイムチヤート図、第３図は本考
案を実施した全体説明図である。
１……第１の処理装置、１−１……ペンタツチ
入力装置、２……第２の処理装置、３……インタ
ーフエース装置、４……発振器、５……クロツク
パルス発生部、６……入力部、７……タイミング
生成部、８……パリテイ付加回路、９……出力部
、１０……メモリ、２０，２１……接続線、ａ…
…クロツクパルス、ｂ……８ビツトパラレルデー
タ、ｃ……シリアルデータ、ｄ……メモリ書込パ
ルス、ｅ……偶数パリテイビツト、ｆ……データ
パルス。
FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a time chart of the embodiment of the present invention, and FIG. 3 is an overall explanatory diagram of the embodiment of the present invention. 1... First processing device, 1-1... Pen-touch input device, 2... Second processing device, 3... Interface device, 4... Oscillator, 5... Clock pulse generation section, 6... Input Part, 7... Timing generation part, 8... Parity addition circuit, 9... Output part, 10... Memory, 20, 21... Connection line, a...
...clock pulse, b...8-bit parallel data, c...serial data, d...memory write pulse, e...even parity bit, f...data pulse.
Claims (1)
部とを備えた第１の処理装置と、 端末装置として構成される第２の処理装置を有
し、 該第１の処理装置のデータ出力部に設置される
パラレルインタフエースと前記第２の処理装置の
入力用シリアルインターフエスとの間において、 データのパラレル−シリアル変換を行う手段と 前記第１の処理装置のパラレルインタフエース
と前記第２の処理装置のシリアルインターフエー
スとを整合・接続する手段を有するインターフエ
ース装置であつて、 前記第１の処理装置のデータ出力部のパラレル
データをパラレル−シリアル変換し、 前記第２の処理装置に入力するシリアルデータ
について シリアルデータの先頭にスタートビツトを付加
する手段と シリアルデータの尾部にストツプビツトを付加
する手段と 該スタートビツトに続いて誤り訂正のためのパ
リテイビツトを付加する手段を 具備してなることを特徴とするインタフエース
装置。[Claims for Utility Model Registration] A first processing device comprising a data input section, a data processing section, and a data output section; and a second processing device configured as a terminal device; means for performing parallel-to-serial conversion of data between a parallel interface installed in a data output section of the processing device and an input serial interface of the second processing device; and a parallel interface of the first processing device. An interface device comprising means for matching and connecting an interface and a serial interface of the second processing device, the interface device comprising: converting parallel data from a data output section of the first processing device from parallel to serial; Concerning the serial data input to the second processing device, means for adding a start bit to the beginning of the serial data, means for adding a stop bit to the tail of the serial data, and means for adding a parity bit for error correction following the start bit. An interface device comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10448587U JPS6410826U (en) | 1987-07-09 | 1987-07-09 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10448587U JPS6410826U (en) | 1987-07-09 | 1987-07-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6410826U true JPS6410826U (en) | 1989-01-20 |
Family
ID=31336243
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10448587U Pending JPS6410826U (en) | 1987-07-09 | 1987-07-09 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6410826U (en) |
-
1987
- 1987-07-09 JP JP10448587U patent/JPS6410826U/ja active Pending
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